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| author | Matt Roper <matthew.d.roper@intel.com> | 2026-02-06 01:05:09 +0300 |
|---|---|---|
| committer | Matt Roper <matthew.d.roper@intel.com> | 2026-02-10 18:41:48 +0300 |
| commit | e04c609eedf4d6748ac0bcada4de1275b034fed6 (patch) | |
| tree | 3fa88a8570f6c1fe824c216ff4d35227a5f68280 /include | |
| parent | d2e0540a62693f324d8e1f5ad7440994350cd998 (diff) | |
| download | linux-e04c609eedf4d6748ac0bcada4de1275b034fed6.tar.xz | |
drm/xe/xe2_hpg: Fix handling of Wa_14019988906 & Wa_14019877138
The PSS_CHICKEN register has been part of the RCS engine's LRC since it
was first introduced in Xe_LP. That means that any workarounds that
adjust its value (such as Wa_14019988906 and Wa_14019877138) need to be
implemented in the lrc_was[] table so that they become part of the
default LRC from which all subsequent LRCs are copied. Although these
workarounds were implemented correctly on most platforms, they were
incorrectly placed on the engine_was[] table for Xe2_HPG.
Move the workarounds to the proper lrc_was[] table and switch the
'xe_rtp_match_first_render_or_compute' rule to specifically match the
RCS since that's the engine whose LRC manages the register.
Bspec: 65182
Fixes: 7f3ee7d88058 ("drm/xe/xe2hpg: Add initial GT workarounds")
Reviewed-by: Shekhar Chauhan <shekhar.chauhan@intel.com>
Link: https://patch.msgid.link/20260205220508.51905-2-matthew.d.roper@intel.com
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Diffstat (limited to 'include')
0 files changed, 0 insertions, 0 deletions