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| author | Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> | 2026-05-20 17:51:22 +0300 |
|---|---|---|
| committer | Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> | 2026-05-22 16:43:13 +0300 |
| commit | ddbcc8750043039a8f1a6f6cbef705cf1851f81a (patch) | |
| tree | ca51247b08abcc0ae4732327786359f982634f14 /include | |
| parent | 86ec9084a27370306fa07753bb8938a327cf00fa (diff) | |
| download | linux-ddbcc8750043039a8f1a6f6cbef705cf1851f81a.tar.xz | |
drm/msm/adreno: write reserved UBWC-related bits
On the latest A8xx Adreno chips several of the bits in the UBWC-related
registers are now hardwired to 1. Currently the driver doesn't write
them because there is no side-effect. In the preparation for the
refactoring in the next patch, write '1' to those bits anyway.
Reviewed-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/726504/
Link: https://lore.kernel.org/r/20260520-ubwc-rework-v5-15-72f2749bc807@oss.qualcomm.com
Diffstat (limited to 'include')
0 files changed, 0 insertions, 0 deletions