diff options
| author | Devendra K Verma <devendra.verma@amd.com> | 2026-03-18 10:04:03 +0300 |
|---|---|---|
| committer | Vinod Koul <vkoul@kernel.org> | 2026-03-18 12:41:40 +0300 |
| commit | b7560798466a07d9c3fb011698e92c335ab28baf (patch) | |
| tree | 893c6fe3c2f1408edb650f9ae5c4d780f3b3deed /include | |
| parent | 14eb9a1d338fdc301a2297af86818ecf716b1539 (diff) | |
| download | linux-b7560798466a07d9c3fb011698e92c335ab28baf.tar.xz | |
dmaengine: dw-edma: Add non-LL mode
AMD MDB IP supports Linked List (LL) mode as well as non-LL mode.
The current code does not have the mechanisms to enable the
DMA transactions using the non-LL mode. The following two cases
are added with this patch:
- For the AMD (Xilinx) only, when a valid physical base address of
the device side DDR is not configured, then the IP can still be
used in non-LL mode. For all the channels DMA transactions will
be using the non-LL mode only. This, the default non-LL mode,
is not applicable for Synopsys IP with the current code addition.
- If the default mode is LL-mode, for both AMD (Xilinx) and Synosys,
and if user wants to use non-LL mode then user can do so via
configuring the peripheral_config param of dma_slave_config.
Signed-off-by: Devendra K Verma <devendra.verma@amd.com>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Link: https://patch.msgid.link/20260318070403.1634706-3-devendra.verma@amd.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Diffstat (limited to 'include')
| -rw-r--r-- | include/linux/dma/edma.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/include/linux/dma/edma.h b/include/linux/dma/edma.h index 9da53c75e49b..1fafd5b0e315 100644 --- a/include/linux/dma/edma.h +++ b/include/linux/dma/edma.h @@ -103,6 +103,7 @@ struct dw_edma_chip { enum dw_edma_map_format mf; struct dw_edma *dw; + bool cfg_non_ll; }; /* Export to the platform drivers */ |