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authorArnd Bergmann <arnd@arndb.de>2026-05-20 13:12:33 +0300
committerArnd Bergmann <arnd@arndb.de>2026-05-20 13:12:38 +0300
commitae6bbc1ef58c77133307225102c7e84dd2d98fff (patch)
treedeb413a5e09dac1f912beafc35d93f4b3cad9145 /include
parent6cf3cf025848f2b13ddf1db0577a5f178492a3ff (diff)
parent44f1ef06ceec55b7704c7d773d6136ca8b90f8b7 (diff)
downloadlinux-ae6bbc1ef58c77133307225102c7e84dd2d98fff.tar.xz
Merge tag 'renesas-dts-for-v7.2-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/dt
Renesas DTS updates for v7.2 - Add GPU support for R-Car M3-W(+)-based ULCB and Salvator-X(S) development boards, - Add Ethernet, OPP table, interrupt, pin control, and watchdog support for the RZ/G3L SoC and the RZ/G3L SMARC SoM board, - Add Coresight support for the R-Mobile A1 and APE6 SoCs, and the Armadillo-800 EVA and APE6EVM development boards, - Miscellaneous fixes and improvements. * tag 'renesas-dts-for-v7.2-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel: (40 commits) ARM: dts: renesas: r8a73a4: Describe coresight on R-Mobile APE6 ARM: dts: renesas: r8a73a4: Add ZT/ZTR trace clock on R-Mobile APE6 dt-bindings: clock: renesas,cpg-clocks: Document ZT/ZTR trace clock on R-Mobile APE6 arm64: dts: renesas: rzg3l-smarc-som: Enable watchdog arm64: dts: renesas: r9a08g046: Add wdt device node arm64: dts: renesas: salvator-common: Sort sound node arm64: dts: renesas: ebisu: Sort sound node arm64: dts: renesas: gray-hawk-single: Fix AVB0 PHY node alignment arm64: dts: renesas: rzg3l-smarc-som: Enable eth1 (GBETH1) interface arm64: dts: renesas: rzg3l-smarc-som: Add pinctrl configuration for ETH0 arm64: dts: renesas: r9a08g046l48-smarc: Add SCIF0 pincontrol arm64: dts: renesas: r9a08g046: Add pincontrol node arm64: dts: renesas: r9a08g046: Add ICU node arm64: dts: renesas: r9a08g046: Add OPP table arm64: dts: renesas: Add pinctrl reset-names for RZ/G2L and RZ/V2H family SoCs ARM: dts: renesas: r8a7740: Describe coresight ARM: dts: renesas: r8a7740: Add ZT/ZTR trace clocks arm64: dts: renesas: rzg3l-smarc-som: Enable eth0 (GBETH0) interface arm64: dts: renesas: r9a08g046: Add GBETH nodes arm64: dts: renesas: r8a77961-salvator-xs: Enable GPU support ... Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'include')
-rw-r--r--include/dt-bindings/clock/r8a73a4-clock.h2
-rw-r--r--include/dt-bindings/clock/r8a7740-clock.h2
-rw-r--r--include/dt-bindings/pinctrl/renesas,r9a08g046-pinctrl.h38
3 files changed, 42 insertions, 0 deletions
diff --git a/include/dt-bindings/clock/r8a73a4-clock.h b/include/dt-bindings/clock/r8a73a4-clock.h
index 655440a3e7c6..028ecef81451 100644
--- a/include/dt-bindings/clock/r8a73a4-clock.h
+++ b/include/dt-bindings/clock/r8a73a4-clock.h
@@ -23,6 +23,8 @@
#define R8A73A4_CLK_ZX 13
#define R8A73A4_CLK_ZS 14
#define R8A73A4_CLK_HP 15
+#define R8A73A4_CLK_ZTR 16
+#define R8A73A4_CLK_ZT 17
/* MSTP1 */
#define R8A73A4_CLK_TMU0 25
diff --git a/include/dt-bindings/clock/r8a7740-clock.h b/include/dt-bindings/clock/r8a7740-clock.h
index 1b3fdb39cc42..8a8816b2ff6a 100644
--- a/include/dt-bindings/clock/r8a7740-clock.h
+++ b/include/dt-bindings/clock/r8a7740-clock.h
@@ -24,6 +24,8 @@
#define R8A7740_CLK_ZB 14
#define R8A7740_CLK_M3 15
#define R8A7740_CLK_CP 16
+#define R8A7740_CLK_ZTR 17
+#define R8A7740_CLK_ZT 18
/* MSTP1 */
#define R8A7740_CLK_CEU21 28
diff --git a/include/dt-bindings/pinctrl/renesas,r9a08g046-pinctrl.h b/include/dt-bindings/pinctrl/renesas,r9a08g046-pinctrl.h
new file mode 100644
index 000000000000..5ec5bfc27c7d
--- /dev/null
+++ b/include/dt-bindings/pinctrl/renesas,r9a08g046-pinctrl.h
@@ -0,0 +1,38 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * This header provides constants for Renesas RZ/G3L family pinctrl bindings.
+ *
+ * Copyright (C) 2026 Renesas Electronics Corp.
+ *
+ */
+
+#ifndef __DT_BINDINGS_PINCTRL_RENESAS_R9A08G046_PINCTRL_H__
+#define __DT_BINDINGS_PINCTRL_RENESAS_R9A08G046_PINCTRL_H__
+
+#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
+
+/* RZG3L_Px = Offset address of PFC_P_mn - 0x22 */
+#define RZG3L_P2 2
+#define RZG3L_P3 3
+#define RZG3L_P5 5
+#define RZG3L_P6 6
+#define RZG3L_P7 7
+#define RZG3L_P8 8
+#define RZG3L_PA 10
+#define RZG3L_PB 11
+#define RZG3L_PC 12
+#define RZG3L_PD 13
+#define RZG3L_PE 14
+#define RZG3L_PF 15
+#define RZG3L_PG 16
+#define RZG3L_PH 17
+#define RZG3L_PJ 19
+#define RZG3L_PK 20
+#define RZG3L_PL 21
+#define RZG3L_PM 22
+#define RZG3L_PS 28
+
+#define RZG3L_PORT_PINMUX(b, p, f) RZG2L_PORT_PINMUX(RZG3L_P##b, p, f)
+#define RZG3L_GPIO(port, pin) RZG2L_GPIO(RZG3L_P##port, pin)
+
+#endif /* __DT_BINDINGS_PINCTRL_RENESAS_R9A08G046_PINCTRL_H__ */