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authorSriharsha Basavapatna <sriharsha.basavapatna@broadcom.com>2026-03-02 14:00:36 +0300
committerJason Gunthorpe <jgg@nvidia.com>2026-03-08 13:20:25 +0300
commita06165a705eefff4b524ad72c50c9ad82bdf4fae (patch)
treea6c2ffdc86215494c3f8c958f16cfb5398f2e199 /include
parentcec5157b6c73e3e43ce868b7726dfece8891c1f8 (diff)
downloadlinux-a06165a705eefff4b524ad72c50c9ad82bdf4fae.tar.xz
RDMA/bnxt_re: Support application specific CQs
This patch supports application allocated memory for CQs. The application allocates and manages the CQs directly. To support this, the driver exports a new comp_mask to indicate direct control of the CQ. When this comp_mask bit is set in the ureq, the driver maps this application allocated CQ memory into hardware. As the application manages this memory, the CQ depth ('cqe') passed by it must be used as is and the driver shouldn't update it. For CQs, ib_core supports pinning dmabuf based application memory, specified through provider attributes. This umem is mananged by the ib_core and is available in ib_cq. Register 'create_cq_user' devop to process this umem. The driver also supports the legacy interface that allocates umem internally. Link: https://patch.msgid.link/r/20260302110036.36387-7-sriharsha.basavapatna@broadcom.com Signed-off-by: Sriharsha Basavapatna <sriharsha.basavapatna@broadcom.com> Reviewed-by: Selvin Xavier <selvin.xavier@broadcom.com> Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
Diffstat (limited to 'include')
-rw-r--r--include/uapi/rdma/bnxt_re-abi.h7
1 files changed, 6 insertions, 1 deletions
diff --git a/include/uapi/rdma/bnxt_re-abi.h b/include/uapi/rdma/bnxt_re-abi.h
index ef14e24836b1..40955eaba32e 100644
--- a/include/uapi/rdma/bnxt_re-abi.h
+++ b/include/uapi/rdma/bnxt_re-abi.h
@@ -102,12 +102,17 @@ struct bnxt_re_pd_resp {
struct bnxt_re_cq_req {
__aligned_u64 cq_va;
__aligned_u64 cq_handle;
+ __aligned_u64 comp_mask;
};
-enum bnxt_re_cq_mask {
+enum bnxt_re_resp_cq_mask {
BNXT_RE_CQ_TOGGLE_PAGE_SUPPORT = 0x1,
};
+enum bnxt_re_req_cq_mask {
+ BNXT_RE_CQ_FIXED_NUM_CQE_ENABLE = 0x1,
+};
+
struct bnxt_re_cq_resp {
__u32 cqid;
__u32 tail;