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authorJason Gunthorpe <jgg@nvidia.com>2026-05-08 17:53:06 +0300
committerJoerg Roedel <joerg.roedel@amd.com>2026-05-19 11:48:09 +0300
commit835d06ee7ef0c2fc2adcf5bae5355c8bad900c21 (patch)
tree0ff5fb23378a1611963f64d19f1a8684539ddb1e /include
parente4084c6bbb42b0ef2dbfceca70513cc1f49aff61 (diff)
downloadlinux-835d06ee7ef0c2fc2adcf5bae5355c8bad900c21.tar.xz
iommu/riscv: Include the dword number in RISCV_IOMMU_CMD macros
The command queue entry format is 128 bits. Follow the pattern of the other drivers and encode the 64 bit dword number in the macro itself. RISC-V further has similarly named macros that are not field layout macros, but field content macros which won't get a new number. Overall this is clearer to understand the code and check for errors like using the wrong macro in the wrong spot. Signed-off-by: Jason Gunthorpe <jgg@nvidia.com> Reviewed-by: Tomasz Jeznach <tjeznach@rivosinc.com> Tested-by: Andrew Jones <andrew.jones@oss.qualcomm.com> Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
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