diff options
| author | Yao Zi <ziyao@disroot.org> | 2025-09-19 17:26:42 +0300 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2025-09-21 22:48:30 +0300 |
| commit | 793e6b74806eea39da26f2fb7e4b640608d9598d (patch) | |
| tree | 8fb6dd30d3bc10948c052b028ec287cf03deb0c5 /include | |
| parent | 8f5ae30d69d7543eee0d70083daf4de8fe15d585 (diff) | |
| download | linux-793e6b74806eea39da26f2fb7e4b640608d9598d.tar.xz | |
dt-bindings: clock: loongson2: Add Loongson-2K0300 compatible
Document the clock controller shipped in Loongson-2K0300 SoC, which
generates various clock signals for SoC peripherals. Differing from
previous generations of SoCs, LS2K0300 requires a 120MHz external clock
input.
Signed-off-by: Yao Zi <ziyao@disroot.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Yanteng Si <siyanteng@cqsoftware.com.cn>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'include')
| -rw-r--r-- | include/dt-bindings/clock/loongson,ls2k-clk.h | 36 |
1 files changed, 36 insertions, 0 deletions
diff --git a/include/dt-bindings/clock/loongson,ls2k-clk.h b/include/dt-bindings/clock/loongson,ls2k-clk.h index 4279ba595f1e..8cbb86b2cf1e 100644 --- a/include/dt-bindings/clock/loongson,ls2k-clk.h +++ b/include/dt-bindings/clock/loongson,ls2k-clk.h @@ -43,4 +43,40 @@ #define LOONGSON2_I2S_CLK 33 #define LOONGSON2_MISC_CLK 34 +#define LS2K0300_CLK_STABLE 0 +#define LS2K0300_NODE_PLL 1 +#define LS2K0300_DDR_PLL 2 +#define LS2K0300_PIX_PLL 3 +#define LS2K0300_CLK_THSENS 4 +#define LS2K0300_CLK_NODE_DIV 5 +#define LS2K0300_CLK_NODE_PLL_GATE 6 +#define LS2K0300_CLK_NODE_SCALE 7 +#define LS2K0300_CLK_NODE_GATE 8 +#define LS2K0300_CLK_GMAC_DIV 9 +#define LS2K0300_CLK_GMAC_GATE 10 +#define LS2K0300_CLK_I2S_DIV 11 +#define LS2K0300_CLK_I2S_SCALE 12 +#define LS2K0300_CLK_I2S_GATE 13 +#define LS2K0300_CLK_DDR_DIV 14 +#define LS2K0300_CLK_DDR_GATE 15 +#define LS2K0300_CLK_NET_DIV 16 +#define LS2K0300_CLK_NET_GATE 17 +#define LS2K0300_CLK_DEV_DIV 18 +#define LS2K0300_CLK_DEV_GATE 19 +#define LS2K0300_CLK_PIX_DIV 20 +#define LS2K0300_CLK_PIX_PLL_GATE 21 +#define LS2K0300_CLK_PIX_SCALE 22 +#define LS2K0300_CLK_PIX_GATE 23 +#define LS2K0300_CLK_GMACBP_DIV 24 +#define LS2K0300_CLK_GMACBP_GATE 25 +#define LS2K0300_CLK_USB_SCALE 26 +#define LS2K0300_CLK_USB_GATE 27 +#define LS2K0300_CLK_APB_SCALE 28 +#define LS2K0300_CLK_APB_GATE 29 +#define LS2K0300_CLK_BOOT_SCALE 30 +#define LS2K0300_CLK_BOOT_GATE 31 +#define LS2K0300_CLK_SDIO_SCALE 32 +#define LS2K0300_CLK_SDIO_GATE 33 +#define LS2K0300_CLK_GMAC_IN 34 + #endif |