Merge tag 'soc-drivers-7.2' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

Pull SoC driver updates from Arnd Bergmann:
 "There are a few added drivers, but mostly the normal maintenance to
  drivers for firmware, memory controller and other soc specific
  hardware:

   - The NXP QuickEngine gets modern MSI support, which allows some
     cleanups to the GICv3 irqchip chip driver

   - A new SoC specific driver for the Renesas R-Car MFIS unit is added,
     encapsulating support for the on-chip mailbox and hwspinlock
     implementations that are not easily separated into individual
     drivers

   - The Qualcomm SoC drivers add support for additional SoC
     implementations, and flexibility around power management for the
     serial-engine driver as well as probing the LLCC driver using
     custom hardware descriptions inside of the device itself.

   - Added support for the Samsung thermal management unit

   - A cleanup to the Tegra 'PMC' driver interfaces to remove legacy
     APIs and allow multiple PMC instances everywhere.

   - Updates to the TI SCI and KNAS drivers to improve suspend/resume
     support.

   - Minor driver changes for mediatek, xilinx, allwinner, aspeed,
     tegra, broadcom, amd, microchip and starfive specific drivers

   - Memory controller updates for Tegra and Renesas for additional SoC
     types and other improvements.

   - Firmware driver updates for Arm FF-A, SMCCC and SCMI interfaces, to
     update driver probing, object lifetimes and address minor bugs"

* tag 'soc-drivers-7.2' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (189 commits)
  Revert "firmware: zynqmp: Add dynamic CSU register discovery and sysfs interface"
  Revert "Documentation: ABI: add sysfs interface for ZynqMP CSU registers"
  memory: tegra234: drop dead NULL check in tegra234_mc_icc_aggregate()
  memory: tegra264: drop redundant tegra264_mc_icc_aggregate()
  memory: tegra186-emc: stop borrowing MC aggregate hook for EMC
  soc: aspeed: cleanup dead default for ASPEED_SOCINFO
  firmware: tegra: bpmp: Add support for multi-socket platforms
  firmware: tegra: bpmp: Propagate debugfs errors
  soc/tegra: pmc: Add Tegra238 support
  soc/tegra: pmc: Restrict power-off handler to Nexus 7
  soc/tegra: pmc: Populate powergate debugfs only when needed
  soc/tegra: pmc: Move legacy code behind CONFIG_ARM guard
  soc/tegra: pmc: Remove unused legacy functions
  soc/tegra: pmc: Create PMC context dynamically
  firmware: samsung: acpm: remove compile-testing stubs
  firmware: samsung: acpm: Add devm_acpm_get_by_phandle helper
  firmware: samsung: acpm: Add TMU protocol support
  firmware: samsung: acpm: Make acpm_ops const and access via pointer
  firmware: samsung: acpm: Drop redundant _ops suffix in acpm_ops members
  firmware: samsung: acpm: Annotate rx_data->cmd with __counted_by_ptr
  ...

18 files changed, 545 insertions, 129 deletions

diff --git a/include/dt-bindings/arm/qcom,ids.h b/include/dt-bindings/arm/qcom,ids.h
index 336f7bb7188a..1af73c0ad41c 100644
--- a/include/dt-bindings/arm/qcom,ids.h
+++ b/include/dt-bindings/arm/qcom,ids.h
@@ -290,6 +290,7 @@
 #define QCOM_ID_IPQ5424			651
 #define QCOM_ID_QCM6690			657
 #define QCOM_ID_QCS6690			658
+#define QCOM_ID_SM7750			659
 #define QCOM_ID_SM8850			660
 #define QCOM_ID_IPQ5404			671
 #define QCOM_ID_QCS9100			667
@@ -297,13 +298,23 @@
 #define QCOM_ID_QCS8275			675
 #define QCOM_ID_QCS9075			676
 #define QCOM_ID_QCS615			680
+#define QCOM_ID_SA8797P			690
 #define QCOM_ID_CQ7790M			731
 #define QCOM_ID_CQ7790S			732
+#define QCOM_ID_CQ2390M			756
+#define QCOM_ID_CQ2390S			758
+#define QCOM_ID_IQ2390S			759
 #define QCOM_ID_IPQ5200			765
 #define QCOM_ID_IPQ5210			766
 #define QCOM_ID_QCF2200			767
 #define QCOM_ID_QCF3200			768
 #define QCOM_ID_QCF3210			769
+#define QCOM_ID_IPQ9620			770
+#define QCOM_ID_IPQ9650			771
+#define QCOM_ID_IPQ9610			778
+#define QCOM_ID_IPQ9630			779
+#define QCOM_ID_IPQ9640			780
+#define QCOM_ID_IPQ9670			781
 
 /*
  * The board type and revision information, used by Qualcomm bootloaders and
diff --git a/include/dt-bindings/memory/nvidia,tegra238-mc.h b/include/dt-bindings/memory/nvidia,tegra238-mc.h
new file mode 100644
index 000000000000..be24c0eb3f15
--- /dev/null
+++ b/include/dt-bindings/memory/nvidia,tegra238-mc.h
@@ -0,0 +1,74 @@
+/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
+/* Copyright (c) 2026, NVIDIA CORPORATION. All rights reserved. */
+
+#ifndef DT_BINDINGS_MEMORY_TEGRA238_MC_H
+#define DT_BINDINGS_MEMORY_TEGRA238_MC_H
+
+/* special clients */
+#define TEGRA238_SID_INVALID		0x0
+#define TEGRA238_SID_PASSTHROUGH	0x7f
+
+/* ISO stream IDs */
+#define TEGRA238_SID_ISO_NVDISPLAY	0x1
+#define TEGRA238_SID_ISO_APE0		0x2
+#define TEGRA238_SID_ISO_APE1		0x3
+
+/* NISO stream IDs */
+#define TEGRA238_SID_AON		0x1
+#define TEGRA238_SID_BPMP		0x2
+#define TEGRA238_SID_ETR		0x3
+#define TEGRA238_SID_FDE		0x4
+#define TEGRA238_SID_HC		0x5
+#define TEGRA238_SID_HDA		0x6
+#define TEGRA238_SID_NVDEC		0x7
+#define TEGRA238_SID_NVDISPLAY		0x8
+#define TEGRA238_SID_NVENC		0x9
+#define TEGRA238_SID_OFA		0xa
+#define TEGRA238_SID_PCIE0		0xb
+#define TEGRA238_SID_PCIE1		0xc
+#define TEGRA238_SID_PCIE2		0xd
+#define TEGRA238_SID_PCIE3		0xe
+#define TEGRA238_SID_HWMP_PMA		0xf
+#define TEGRA238_SID_PSC		0x10
+#define TEGRA238_SID_SDMMC1A		0x11
+#define TEGRA238_SID_SDMMC4A		0x12
+#define TEGRA238_SID_SES_SE0		0x13
+#define TEGRA238_SID_SES_SE1		0x14
+#define TEGRA238_SID_SES_SE2		0x15
+#define TEGRA238_SID_SEU1_SE0		0x16
+#define TEGRA238_SID_SEU1_SE1		0x17
+#define TEGRA238_SID_SEU1_SE2		0x18
+#define TEGRA238_SID_TSEC		0x19
+#define TEGRA238_SID_UFSHC		0x1a
+#define TEGRA238_SID_VIC		0x1b
+#define TEGRA238_SID_XUSB_HOST		0x1c
+#define TEGRA238_SID_XUSB_DEV		0x1d
+#define TEGRA238_SID_GPCDMA_0		0x1e
+#define TEGRA238_SID_SMMU_TEST		0x1f
+
+/* Host1x virtualization clients. */
+#define TEGRA238_SID_HOST1X_CTX0	0x20
+#define TEGRA238_SID_HOST1X_CTX1	0x21
+#define TEGRA238_SID_HOST1X_CTX2	0x22
+#define TEGRA238_SID_HOST1X_CTX3	0x23
+#define TEGRA238_SID_HOST1X_CTX4	0x24
+#define TEGRA238_SID_HOST1X_CTX5	0x25
+#define TEGRA238_SID_HOST1X_CTX6	0x26
+#define TEGRA238_SID_HOST1X_CTX7	0x27
+
+#define TEGRA238_SID_XUSB_VF0		0x28
+#define TEGRA238_SID_XUSB_VF1		0x29
+#define TEGRA238_SID_XUSB_VF2		0x2a
+#define TEGRA238_SID_XUSB_VF3		0x2b
+
+/* Host1x command buffers */
+#define TEGRA238_SID_HC_VM0		0x2c
+#define TEGRA238_SID_HC_VM1		0x2d
+#define TEGRA238_SID_HC_VM2		0x2e
+#define TEGRA238_SID_HC_VM3		0x2f
+#define TEGRA238_SID_HC_VM4		0x30
+#define TEGRA238_SID_HC_VM5		0x31
+#define TEGRA238_SID_HC_VM6		0x32
+#define TEGRA238_SID_HC_VM7		0x33
+
+#endif
diff --git a/include/dt-bindings/memory/nvidia,tegra264.h b/include/dt-bindings/memory/nvidia,tegra264.h
index 521405c01f84..c65403a76413 100644
--- a/include/dt-bindings/memory/nvidia,tegra264.h
+++ b/include/dt-bindings/memory/nvidia,tegra264.h
@@ -58,24 +58,108 @@
  * memory client IDs
  */
 
+/* PTW read client mapped to SOC SMMU0 */
+#define TEGRA264_MEMORY_CLIENT_PTCR		0x00
 /* HOST1X read client */
 #define TEGRA264_MEMORY_CLIENT_HOST1XR		0x16
+#define TEGRA264_MEMORY_CLIENT_MPCORER		0x27
+/* Platform security (PSC) Read clients */
+#define TEGRA264_MEMORY_CLIENT_PSCR		0x33
+/* PSC Write clients */
+#define TEGRA264_MEMORY_CLIENT_PSCW		0x34
+/* ISP0 Read client */
+#define TEGRA264_MEMORY_CLIENT_ISP0R		0x37
+#define TEGRA264_MEMORY_CLIENT_MPCOREW		0x39
+/* ISP0 Write client */
+#define TEGRA264_MEMORY_CLIENT_ISP0W		0x44
+/* ISP1 Write client */
+#define TEGRA264_MEMORY_CLIENT_ISP1W		0x45
+/* ISP FALCON Read client */
+#define TEGRA264_MEMORY_CLIENT_ISPFALCONR	0x47
+/* ISP FALCON Write client */
+#define TEGRA264_MEMORY_CLIENT_ISPFALCONW	0x4f
+/* MGBE2 Read mccif */
+#define TEGRA264_MEMORY_CLIENT_MGBE2R		0x5c
+#define TEGRA264_MEMORY_CLIENT_OFAR2MC		0x5d
+#define TEGRA264_MEMORY_CLIENT_OFAW2MC		0x5e
+/* MGBE2 Write mccif */
+#define TEGRA264_MEMORY_CLIENT_MGBE2W		0x5f
+/* MGBE3 Read mccif */
+#define TEGRA264_MEMORY_CLIENT_MGBE3R		0x61
+/* MGBE3 Write mccif */
+#define TEGRA264_MEMORY_CLIENT_MGBE3W		0x65
+/* SEU1 Memory Read Client */
+#define TEGRA264_MEMORY_CLIENT_SEU1RD		0x68
+/* SEU1 Memory Write Client */
+#define TEGRA264_MEMORY_CLIENT_SEU1WR		0x69
 /* VIC read client */
 #define TEGRA264_MEMORY_CLIENT_VICR		0x6c
 /* VIC Write client */
 #define TEGRA264_MEMORY_CLIENT_VICW		0x6d
 /* VI R5 Write client */
 #define TEGRA264_MEMORY_CLIENT_VIW		0x72
+/* QSPI Read Client */
+#define TEGRA264_MEMORY_CLIENT_XSPI0R		0x75
+/* QSPI Write Client */
+#define TEGRA264_MEMORY_CLIENT_XSPI0W		0x76
 #define TEGRA264_MEMORY_CLIENT_NVDECSRD2MC	0x78
 #define TEGRA264_MEMORY_CLIENT_NVDECSWR2MC	0x79
 /* Audio processor(APE) Read client */
 #define TEGRA264_MEMORY_CLIENT_APER		0x7a
 /* Audio processor(APE) Write client */
 #define TEGRA264_MEMORY_CLIENT_APEW		0x7b
+/* SEU0 read client */
+#define TEGRA264_MEMORY_CLIENT_SER		0x80
+/* SEU0 write client */
+#define TEGRA264_MEMORY_CLIENT_SEW		0x81
+/* AXI AP and DFD/Coresight1-AUX0/1 Read clients both share the same interface on MSS */
+#define TEGRA264_MEMORY_CLIENT_AXIAPR		0x82
+/* AXI AP and DFD/Coresight1-AUX0/1 Write clients both share the same interface on MSS */
+#define TEGRA264_MEMORY_CLIENT_AXIAPW		0x83
+/* ETR or DFD/Coresight0 Read Client */
+#define TEGRA264_MEMORY_CLIENT_ETRR		0x84
+/* ETR or DFD/Coresight0 Write Client */
+#define TEGRA264_MEMORY_CLIENT_ETRW		0x85
+/* Security(tsec) Read client */
+#define TEGRA264_MEMORY_CLIENT_TSECR		0x86
+/* Security(tsec) Write client */
+#define TEGRA264_MEMORY_CLIENT_TSECW		0x87
+/* BPMP read client */
+#define TEGRA264_MEMORY_CLIENT_BPMPR		0x93
+/* BPMP write client */
+#define TEGRA264_MEMORY_CLIENT_BPMPW		0x94
+/* AON Read Client */
+#define TEGRA264_MEMORY_CLIENT_AONR		0x97
+/* AON write client */
+#define TEGRA264_MEMORY_CLIENT_AONW		0x98
+/* GPCDMA debug Read client */
+#define TEGRA264_MEMORY_CLIENT_GPCDMAR		0x99
+/* GPCDMA debug Write client */
+#define TEGRA264_MEMORY_CLIENT_GPCDMAW		0x9a
 /* Audio DMA Read client */
 #define TEGRA264_MEMORY_CLIENT_APEDMAR		0x9f
 /* Audio DMA Write client */
 #define TEGRA264_MEMORY_CLIENT_APEDMAW		0xa0
+/* mss internal memqual MIU0 reads */
+#define TEGRA264_MEMORY_CLIENT_MIU0R		0xa6
+/* mss internal memqual MIU0 writes */
+#define TEGRA264_MEMORY_CLIENT_MIU0W		0xa7
+/* mss internal memqual MIU1 reads */
+#define TEGRA264_MEMORY_CLIENT_MIU1R		0xa8
+/* mss internal memqual MIU1 writes */
+#define TEGRA264_MEMORY_CLIENT_MIU1W		0xa9
+/* mss internal memqual MIU2 reads */
+#define TEGRA264_MEMORY_CLIENT_MIU2R		0xae
+/* mss internal memqual MIU2 writes */
+#define TEGRA264_MEMORY_CLIENT_MIU2W		0xaf
+/* mss internal memqual MIU3 reads */
+#define TEGRA264_MEMORY_CLIENT_MIU3R		0xb0
+/* mss internal memqual MIU3 writes */
+#define TEGRA264_MEMORY_CLIENT_MIU3W		0xb1
+/* mss internal memqual MIU4 reads */
+#define TEGRA264_MEMORY_CLIENT_MIU4R		0xb2
+/* mss internal memqual MIU4 writes */
+#define TEGRA264_MEMORY_CLIENT_MIU4W		0xb3
 #define TEGRA264_MEMORY_CLIENT_GPUR02MC		0xb6
 #define TEGRA264_MEMORY_CLIENT_GPUW02MC		0xb7
 /* VI Falcon Read client */
@@ -86,6 +170,8 @@
 #define TEGRA264_MEMORY_CLIENT_RCER		0xd2
 /* Write client of RCE */
 #define TEGRA264_MEMORY_CLIENT_RCEW		0xd3
+#define TEGRA264_MEMORY_CLIENT_NVENC1SRD2MC	0xd6
+#define TEGRA264_MEMORY_CLIENT_NVENC1SWR2MC	0xd7
 /* PCIE0/MSI Write clients */
 #define TEGRA264_MEMORY_CLIENT_PCIE0W		0xd9
 /* PCIE1/RPX4 Read clients */
@@ -108,16 +194,140 @@
 #define TEGRA264_MEMORY_CLIENT_PCIE5R		0xe2
 /* PCIE5/DMX4 Write clients */
 #define TEGRA264_MEMORY_CLIENT_PCIE5W		0xe3
+/* mss internal memqual MIU5 reads */
+#define TEGRA264_MEMORY_CLIENT_MIU5R		0xfc
+/* mss internal memqual MIU5 writes */
+#define TEGRA264_MEMORY_CLIENT_MIU5W		0xfd
+/* mss internal memqual MIU6 writes */
+#define TEGRA264_MEMORY_CLIENT_MIU6W		0xff
+#define TEGRA264_MEMORY_CLIENT_RISTR		0x100
+#define TEGRA264_MEMORY_CLIENT_RISTW		0x101
+/* OESP (Pluton) Read client */
+#define TEGRA264_MEMORY_CLIENT_OESPR		0x102
+/* OESP (Pluton) Write client */
+#define TEGRA264_MEMORY_CLIENT_OESPW		0x103
+/* mss internal memqual MIU7 writes */
+#define TEGRA264_MEMORY_CLIENT_MIU7W		0x105
+/* mss internal memqual MIU8 reads */
+#define TEGRA264_MEMORY_CLIENT_MIU8R		0x106
+/* mss internal memqual MIU8 writes */
+#define TEGRA264_MEMORY_CLIENT_MIU8W		0x107
+/* mss internal memqual MIU9 reads */
+#define TEGRA264_MEMORY_CLIENT_MIU9R		0x108
+/* mss internal memqual MIU9 writes */
+#define TEGRA264_MEMORY_CLIENT_MIU9W		0x109
+/* HWPM Write Interface */
+#define TEGRA264_MEMORY_CLIENT_PMA0AWR		0x122
+#define TEGRA264_MEMORY_CLIENT_NVJPG1SRD2MC	0x123
+#define TEGRA264_MEMORY_CLIENT_NVJPG1SWR2MC	0x124
+/* CTW read client mapped to SMMU0 */
+#define TEGRA264_MEMORY_CLIENT_SMMU0CTWR	0x12e
+/* CMDQV read client mapped to SMMU0 */
+#define TEGRA264_MEMORY_CLIENT_SMMU0CMDQVR	0x12f
+/* CMDQV write client mapped to SMMU0 */
+#define TEGRA264_MEMORY_CLIENT_SMMU0CMDQVW	0x130
+/* EVNTQ write client mapped to SMMU0 */
+#define TEGRA264_MEMORY_CLIENT_SMMU0EVNTQW	0x131
+/* PTW read client mapped to SMMU1 */
+#define TEGRA264_MEMORY_CLIENT_SMMU1PTWR	0x132
+/* CTW read client mapped to SMMU1 */
+#define TEGRA264_MEMORY_CLIENT_SMMU1CTWR	0x134
+/* CMDQV read client mapped to SMMU1 */
+#define TEGRA264_MEMORY_CLIENT_SMMU1CMDQVR	0x135
+/* CMDQV write client mapped to SMMU1 */
+#define TEGRA264_MEMORY_CLIENT_SMMU1CMDQVW	0x136
+/* EVNTQ write client mapped to SMMU1 */
+#define TEGRA264_MEMORY_CLIENT_SMMU1EVNTQW	0x137
+/* PTW read client mapped to SMMU2 */
+#define TEGRA264_MEMORY_CLIENT_SMMU2PTWR	0x138
+/* CTW read client mapped to SMMU2 */
+#define TEGRA264_MEMORY_CLIENT_SMMU2CTWR	0x13a
+/* CMDQV read client mapped to SMMU2 */
+#define TEGRA264_MEMORY_CLIENT_SMMU2CMDQVR	0x13b
+/* CMDQV write client mapped to SMMU2 */
+#define TEGRA264_MEMORY_CLIENT_SMMU2CMDQVW	0x13c
+/* EVNTQ write client mapped to SMMU2 */
+#define TEGRA264_MEMORY_CLIENT_SMMU2EVNTQW	0x13d
+/* CMDQ read client mapped to SMMU0 */
+#define TEGRA264_MEMORY_CLIENT_SMMU0CMDQR	0x144
+/* CMDQ read client mapped to SMMU1 */
+#define TEGRA264_MEMORY_CLIENT_SMMU1CMDQR	0x145
+/* CMDQ read client mapped to SMMU2 */
+#define TEGRA264_MEMORY_CLIENT_SMMU2CMDQR	0x146
+/* Audio processor1(APE1) Read client */
+#define TEGRA264_MEMORY_CLIENT_APE1R		0x150
+/* Audio processor1(APE1) Write client */
+#define TEGRA264_MEMORY_CLIENT_APE1W		0x151
 /* UFS Read client */
 #define TEGRA264_MEMORY_CLIENT_UFSR		0x15c
 /* UFS write client */
 #define TEGRA264_MEMORY_CLIENT_UFSW		0x15d
+/* XUSB HOST Read Client */
+#define TEGRA264_MEMORY_CLIENT_XUSB_DEVR	0x166
+/* XUSB HOST Write Client */
+#define TEGRA264_MEMORY_CLIENT_XUSB_DEVW	0x167
+/* XUSB SS0 Read Client */
+#define TEGRA264_MEMORY_CLIENT_XUSB_DEV1R	0x168
+/* XUSB SS1 Write Client */
+#define TEGRA264_MEMORY_CLIENT_XUSB_DEV2W	0x169
+/* XUSB SS2 Read Client */
+#define TEGRA264_MEMORY_CLIENT_XUSB_DEV3R	0x16a
+/* XUSB SS2 Write Client */
+#define TEGRA264_MEMORY_CLIENT_XUSB_DEV3W	0x16b
+/* XUSB SS3 Read Client */
+#define TEGRA264_MEMORY_CLIENT_XUSB_DEV4R	0x16c
+/* XUSB SS3 Write Client */
+#define TEGRA264_MEMORY_CLIENT_XUSB_DEV4W	0x16d
+/* XUSB DEV Read Client */
+#define TEGRA264_MEMORY_CLIENT_XUSB_DEV5R	0x16e
+/* XUSB DEV Write Client */
+#define TEGRA264_MEMORY_CLIENT_XUSB_DEV5W	0x16f
+/* DCE Read client */
+#define TEGRA264_MEMORY_CLIENT_DCER		0x17a
+/* DCE Write client */
+#define TEGRA264_MEMORY_CLIENT_DCEW		0x17b
 /* HDA Read client */
 #define TEGRA264_MEMORY_CLIENT_HDAR		0x17c
 /* HDA Write client */
 #define TEGRA264_MEMORY_CLIENT_HDAW		0x17d
+/* DISPNISO read client */
+#define TEGRA264_MEMORY_CLIENT_DISPNISOR	0x17e
+/* DISPNISO write client */
+#define TEGRA264_MEMORY_CLIENT_DISPNISOW	0x17f
+/* XUSB SS0 Write Client */
+#define TEGRA264_MEMORY_CLIENT_XUSB_DEV1W	0x180
+/* XUSB SS1 Read Client */
+#define TEGRA264_MEMORY_CLIENT_XUSB_DEV2R	0x181
 /* Disp ISO Read Client */
 #define TEGRA264_MEMORY_CLIENT_DISPR		0x182
+/* MSSSEQ Read Client */
+#define TEGRA264_MEMORY_CLIENT_MSSSEQR		0x185
+/* MSSSEQ Write Client */
+#define TEGRA264_MEMORY_CLIENT_MSSSEQW		0x186
+/* PTW read client mapped to SMMU3 */
+#define TEGRA264_MEMORY_CLIENT_SMMU3PTWR	0x18b
+/* CTW read client mapped to SMMU3 */
+#define TEGRA264_MEMORY_CLIENT_SMMU3CTWR	0x18d
+/* CMDQV read client mapped to SMMU3 */
+#define TEGRA264_MEMORY_CLIENT_SMMU3CMDQVR	0x18e
+/* CMDQV write client mapped to SMMU3 */
+#define TEGRA264_MEMORY_CLIENT_SMMU3CMDQVW	0x18f
+/* EVNTQ write client mapped to SMMU3 */
+#define TEGRA264_MEMORY_CLIENT_SMMU3EVNTQW	0x190
+/* CMDQ read client mapped to SMMU3 */
+#define TEGRA264_MEMORY_CLIENT_SMMU3CMDQR	0x191
+/* PTW read client mapped to SMMU4 */
+#define TEGRA264_MEMORY_CLIENT_SMMU4PTWR	0x192
+/* CTW read client mapped to SMMU4 */
+#define TEGRA264_MEMORY_CLIENT_SMMU4CTWR	0x194
+/* CMDQV read client mapped to SMMU4 */
+#define TEGRA264_MEMORY_CLIENT_SMMU4CMDQVR	0x195
+/* CMDQV write client mapped to SMMU4 */
+#define TEGRA264_MEMORY_CLIENT_SMMU4CMDQVW	0x196
+/* EVNTQ write client mapped to SMMU4 */
+#define TEGRA264_MEMORY_CLIENT_SMMU4EVNTQW	0x197
+/* CMDQ read client mapped to SMMU4 */
+#define TEGRA264_MEMORY_CLIENT_SMMU4CMDQR	0x198
 /* MGBE0 Read mccif */
 #define TEGRA264_MEMORY_CLIENT_MGBE0R		0x1a2
 /* MGBE0 Write mccif */
@@ -128,9 +338,86 @@
 #define TEGRA264_MEMORY_CLIENT_MGBE1W		0x1a5
 /* VI1 R5 Write client */
 #define TEGRA264_MEMORY_CLIENT_VI1W		0x1a6
+/* VI Falcon1 Read client */
+#define TEGRA264_MEMORY_CLIENT_VIFALCON1R	0x1a7
+/* VI Falcon1 Write client */
+#define TEGRA264_MEMORY_CLIENT_VIFALCON1W	0x1a8
+/* ISP FALCON1 Read client */
+#define TEGRA264_MEMORY_CLIENT_ISPFALCON1R	0x1a9
+/* ISP FALCON1 Write client */
+#define TEGRA264_MEMORY_CLIENT_ISPFALCON1W	0x1aa
+/* Read Client of RCE1 */
+#define TEGRA264_MEMORY_CLIENT_RCE1R		0x1ab
+/* Write client of RCE1 */
+#define TEGRA264_MEMORY_CLIENT_RCE1W		0x1ac
+/* SEU2 Read client */
+#define TEGRA264_MEMORY_CLIENT_SEU2R		0x1ad
+/* SEU2 Write client */
+#define TEGRA264_MEMORY_CLIENT_SEU2W		0x1ae
+/* SEU3 Read client */
+#define TEGRA264_MEMORY_CLIENT_SEU3R		0x1af
+/* SEU3 Write client */
+#define TEGRA264_MEMORY_CLIENT_SEU3W		0x1b0
+/* PVA0 Falcon Read mccif */
+#define TEGRA264_MEMORY_CLIENT_PVA0R		0x1b1
+/* PVA0 Falcon Write mccif */
+#define TEGRA264_MEMORY_CLIENT_PVA0W		0x1b2
+/* PVA1 Read mccif */
+#define TEGRA264_MEMORY_CLIENT_PVA1R		0x1b3
+/* PVA1 Write mccif */
+#define TEGRA264_MEMORY_CLIENT_PVA1W		0x1b4
+/* PVA2 Read mccif */
+#define TEGRA264_MEMORY_CLIENT_PVA2R		0x1b5
+/* PVA2 Write mccif */
+#define TEGRA264_MEMORY_CLIENT_PVA2W		0x1b6
+/* ISP3 Write client */
+#define TEGRA264_MEMORY_CLIENT_ISP3W		0x1b7
+/* ISP2 Read Client */
+#define TEGRA264_MEMORY_CLIENT_ISP2R		0x1b8
+/* ISP2 Write Client */
+#define TEGRA264_MEMORY_CLIENT_ISP2W		0x1b9
+/* EQOS Read mccif */
+#define TEGRA264_MEMORY_CLIENT_EQOSR		0x1bc
+/* EQOS Write mccif */
+#define TEGRA264_MEMORY_CLIENT_EQOSW		0x1bd
+/* FSI0 Read mccif */
+#define TEGRA264_MEMORY_CLIENT_FSI0R		0x1be
+/* FSI0 Write mccif */
+#define TEGRA264_MEMORY_CLIENT_FSI0W		0x1bf
+/* FSI1 Read mccif */
+#define TEGRA264_MEMORY_CLIENT_FSI1R		0x1c0
+/* FSI1 Write mccif */
+#define TEGRA264_MEMORY_CLIENT_FSI1W		0x1c1
 /* SDMMC0 Read mccif */
 #define TEGRA264_MEMORY_CLIENT_SDMMC0R		0x1c2
 /* SDMMC0 Write mccif */
 #define TEGRA264_MEMORY_CLIENT_SDMMC0W		0x1c3
+/* Strongbox (SB) read client */
+#define TEGRA264_MEMORY_CLIENT_SBR		0x1c6
+/* Strongbox (SB) write client */
+#define TEGRA264_MEMORY_CLIENT_SBW		0x1c7
+#define TEGRA264_MEMORY_CLIENT_HSS_MIU0R	0x1c8
+#define TEGRA264_MEMORY_CLIENT_HSS_MIU0W	0x1c9
+#define TEGRA264_MEMORY_CLIENT_HSS_MIU1R	0x1ca
+#define TEGRA264_MEMORY_CLIENT_HSS_MIU1W	0x1cb
+#define TEGRA264_MEMORY_CLIENT_HSS_MIU2R	0x1cc
+#define TEGRA264_MEMORY_CLIENT_HSS_MIU2W	0x1cd
+#define TEGRA264_MEMORY_CLIENT_HSS_MIU3R	0x1ce
+#define TEGRA264_MEMORY_CLIENT_HSS_MIU3W	0x1cf
+#define TEGRA264_MEMORY_CLIENT_HSS_MIU4R	0x1d0
+#define TEGRA264_MEMORY_CLIENT_HSS_MIU4W	0x1d1
+#define TEGRA264_MEMORY_CLIENT_HSS_MIU5R	0x1d2
+#define TEGRA264_MEMORY_CLIENT_HSS_MIU5W	0x1d3
+#define TEGRA264_MEMORY_CLIENT_HSS_MIU6R	0x1d4
+#define TEGRA264_MEMORY_CLIENT_HSS_MIU6W	0x1d5
+#define TEGRA264_MEMORY_CLIENT_HSS_MIU7R	0x1d6
+#define TEGRA264_MEMORY_CLIENT_HSS_MIU7W	0x1d7
+#define TEGRA264_MEMORY_CLIENT_GMMUR2MC		0x1d8
+#define TEGRA264_MEMORY_CLIENT_UCFELAR		0x1d9
+#define TEGRA264_MEMORY_CLIENT_UCFELAW		0x1da
+#define TEGRA264_MEMORY_CLIENT_SLCR		0x1db
+#define TEGRA264_MEMORY_CLIENT_SLCW		0x1dc
+#define TEGRA264_MEMORY_CLIENT_REMOTER		0x1dd
+#define TEGRA264_MEMORY_CLIENT_REMOTEW		0x1de
 
 #endif /* DT_BINDINGS_MEMORY_NVIDIA_TEGRA264_H */
diff --git a/include/linux/arm-smccc.h b/include/linux/arm-smccc.h
index e7195750d21b..4de81848fe2e 100644
--- a/include/linux/arm-smccc.h
+++ b/include/linux/arm-smccc.h
@@ -90,6 +90,11 @@
 			   ARM_SMCCC_SMC_32,				\
 			   0, 2)
 
+#define ARM_SMCCC_ARCH_SOC_ID64						\
+	ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL,				\
+			   ARM_SMCCC_SMC_64,				\
+			   0, 2)
+
 #define ARM_SMCCC_ARCH_WORKAROUND_1					\
 	ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL,				\
 			   ARM_SMCCC_SMC_32,				\
diff --git a/include/linux/arm_ffa.h b/include/linux/arm_ffa.h
index 81e603839c4a..17eca3dfc59e 100644
--- a/include/linux/arm_ffa.h
+++ b/include/linux/arm_ffa.h
@@ -173,7 +173,7 @@ struct ffa_partition_info;
 #if IS_REACHABLE(CONFIG_ARM_FFA_TRANSPORT)
 struct ffa_device *
 ffa_device_register(const struct ffa_partition_info *part_info,
-		    const struct ffa_ops *ops);
+		    const struct ffa_ops *ops, struct device *parent);
 void ffa_device_unregister(struct ffa_device *ffa_dev);
 int ffa_driver_register(struct ffa_driver *driver, struct module *owner,
 			const char *mod_name);
@@ -184,7 +184,7 @@ bool ffa_device_is_valid(struct ffa_device *ffa_dev);
 #else
 static inline struct ffa_device *
 ffa_device_register(const struct ffa_partition_info *part_info,
-		    const struct ffa_ops *ops)
+		    const struct ffa_ops *ops, struct device *parent)
 {
 	return NULL;
 }
diff --git a/include/linux/firmware/samsung/exynos-acpm-protocol.h b/include/linux/firmware/samsung/exynos-acpm-protocol.h
index 13f17dc4443b..c6b35c0ff300 100644
--- a/include/linux/firmware/samsung/exynos-acpm-protocol.h
+++ b/include/linux/firmware/samsung/exynos-acpm-protocol.h
@@ -34,31 +34,41 @@ struct acpm_pmic_ops {
 			  u8 type, u8 reg, u8 chan, u8 value, u8 mask);
 };
 
+struct acpm_tmu_ops {
+	int (*init)(struct acpm_handle *handle, unsigned int acpm_chan_id);
+	int (*read_temp)(struct acpm_handle *handle, unsigned int acpm_chan_id,
+			 u8 tz, int *temp);
+	int (*set_threshold)(struct acpm_handle *handle,
+			     unsigned int acpm_chan_id, u8 tz,
+			     const u8 temperature[8], size_t tlen);
+	int (*set_interrupt_enable)(struct acpm_handle *handle,
+				    unsigned int acpm_chan_id, u8 tz, u8 inten);
+	int (*tz_control)(struct acpm_handle *handle, unsigned int acpm_chan_id,
+			  u8 tz, bool enable);
+	int (*clear_tz_irq)(struct acpm_handle *handle,
+			    unsigned int acpm_chan_id, u8 tz);
+	int (*suspend)(struct acpm_handle *handle, unsigned int acpm_chan_id);
+	int (*resume)(struct acpm_handle *handle, unsigned int acpm_chan_id);
+};
+
 struct acpm_ops {
-	struct acpm_dvfs_ops dvfs_ops;
-	struct acpm_pmic_ops pmic_ops;
+	struct acpm_dvfs_ops dvfs;
+	struct acpm_pmic_ops pmic;
+	struct acpm_tmu_ops tmu;
 };
 
 /**
  * struct acpm_handle - Reference to an initialized protocol instance
- * @ops:
+ * @ops:	pointer to the constant ACPM protocol operations.
  */
 struct acpm_handle {
-	struct acpm_ops ops;
+	const struct acpm_ops *ops;
 };
 
 struct device;
 
-#if IS_ENABLED(CONFIG_EXYNOS_ACPM_PROTOCOL)
 struct acpm_handle *devm_acpm_get_by_node(struct device *dev,
 					  struct device_node *np);
-#else
-
-static inline struct acpm_handle *devm_acpm_get_by_node(struct device *dev,
-							struct device_node *np)
-{
-	return NULL;
-}
-#endif
+struct acpm_handle *devm_acpm_get_by_phandle(struct device *dev);
 
 #endif /* __EXYNOS_ACPM_PROTOCOL_H */
diff --git a/include/linux/fsl/mc.h b/include/linux/fsl/mc.h
index 1da63f2d7040..9f671e87c80c 100644
--- a/include/linux/fsl/mc.h
+++ b/include/linux/fsl/mc.h
@@ -357,9 +357,11 @@ int mc_send_command(struct fsl_mc_io *mc_io, struct fsl_mc_command *cmd);
 
 #ifdef CONFIG_FSL_MC_BUS
 #define dev_is_fsl_mc(_dev) ((_dev)->bus == &fsl_mc_bus_type)
+u32 fsl_mc_get_msi_id(struct device *dev);
 #else
 /* If fsl-mc bus is not present device cannot belong to fsl-mc bus */
 #define dev_is_fsl_mc(_dev) (0)
+#define fsl_mc_get_msi_id(_dev)	(0)
 #endif
 
 /* Macro to check if a device is a container device */
@@ -419,10 +421,6 @@ int __must_check fsl_mc_object_allocate(struct fsl_mc_device *mc_dev,
 
 void fsl_mc_object_free(struct fsl_mc_device *mc_adev);
 
-struct irq_domain *fsl_mc_msi_create_irq_domain(struct fwnode_handle *fwnode,
-						struct msi_domain_info *info,
-						struct irq_domain *parent);
-
 int __must_check fsl_mc_allocate_irqs(struct fsl_mc_device *mc_dev);
 
 void fsl_mc_free_irqs(struct fsl_mc_device *mc_dev);
diff --git a/include/linux/irqdomain_defs.h b/include/linux/irqdomain_defs.h
index 36653e2ee1c9..3a03bdfeeee9 100644
--- a/include/linux/irqdomain_defs.h
+++ b/include/linux/irqdomain_defs.h
@@ -17,7 +17,6 @@ enum irq_domain_bus_token {
 	DOMAIN_BUS_PLATFORM_MSI,
 	DOMAIN_BUS_NEXUS,
 	DOMAIN_BUS_IPI,
-	DOMAIN_BUS_FSL_MC_MSI,
 	DOMAIN_BUS_TI_SCI_INTA_MSI,
 	DOMAIN_BUS_WAKEUP,
 	DOMAIN_BUS_VMD_MSI,
diff --git a/include/linux/scmi_imx_protocol.h b/include/linux/scmi_imx_protocol.h
index 2407d7693b6b..ab867463c08c 100644
--- a/include/linux/scmi_imx_protocol.h
+++ b/include/linux/scmi_imx_protocol.h
@@ -52,6 +52,17 @@ struct scmi_imx_misc_ctrl_notify_report {
 	unsigned int		flags;
 };
 
+
+#define MISC_EXT_INFO_LEN_MAX	4
+struct scmi_imx_misc_reset_reason {
+	bool valid:1;
+	bool orig_valid:1;
+	bool err_valid:1;
+	u32 reason;
+	u32 origin;
+	u32 errid;
+};
+
 struct scmi_imx_misc_proto_ops {
 	int (*misc_ctrl_set)(const struct scmi_protocol_handle *ph, u32 id,
 			     u32 num, u32 *val);
@@ -61,6 +72,9 @@ struct scmi_imx_misc_proto_ops {
 				    u32 ctrl_id, u32 evt_id, u32 flags);
 	int (*misc_syslog)(const struct scmi_protocol_handle *ph, u16 *size,
 			   void *array);
+	int (*misc_reset_reason)(const struct scmi_protocol_handle *ph,
+				 bool system, struct scmi_imx_misc_reset_reason *boot_r,
+				 struct scmi_imx_misc_reset_reason *shut_r, u32 *extinfo);
 };
 
 /* See LMM_ATTRIBUTES in imx95.rst */
diff --git a/include/linux/scmi_protocol.h b/include/linux/scmi_protocol.h
index aafaac1496b0..5ab73b1ab9aa 100644
--- a/include/linux/scmi_protocol.h
+++ b/include/linux/scmi_protocol.h
@@ -15,10 +15,9 @@
 
 #define SCMI_MAX_STR_SIZE		64
 #define SCMI_SHORT_NAME_MAX_SIZE	16
-#define SCMI_MAX_NUM_RATES		16
 
 /**
- * struct scmi_revision_info - version information structure
+ * struct scmi_base_info - version information structure
  *
  * @major_ver: Major ABI version. Change here implies risk of backward
  *	compatibility break.
@@ -31,7 +30,7 @@
  * @vendor_id: A vendor identifier(Null terminated ASCII string)
  * @sub_vendor_id: A sub-vendor identifier(Null terminated ASCII string)
  */
-struct scmi_revision_info {
+struct scmi_base_info {
 	u16 major_ver;
 	u16 minor_ver;
 	u8 num_protocols;
@@ -41,27 +40,23 @@ struct scmi_revision_info {
 	char sub_vendor_id[SCMI_SHORT_NAME_MAX_SIZE];
 };
 
+struct scmi_clock_rates {
+	bool rate_discrete;
+	unsigned int num_rates;
+	u64 *rates;
+};
+
 struct scmi_clock_info {
 	char name[SCMI_MAX_STR_SIZE];
 	unsigned int enable_latency;
-	bool rate_discrete;
 	bool rate_changed_notifications;
 	bool rate_change_requested_notifications;
 	bool state_ctrl_forbidden;
 	bool rate_ctrl_forbidden;
 	bool parent_ctrl_forbidden;
 	bool extended_config;
-	union {
-		struct {
-			int num_rates;
-			u64 rates[SCMI_MAX_NUM_RATES];
-		} list;
-		struct {
-			u64 min_rate;
-			u64 max_rate;
-			u64 step_size;
-		} range;
-	};
+	u64 min_rate;
+	u64 max_rate;
 	int num_parents;
 	u32 *parents;
 };
@@ -91,6 +86,11 @@ enum scmi_clock_oem_config {
  * @info_get: get the information of the specified clock
  * @rate_get: request the current clock rate of a clock
  * @rate_set: set the clock rate of a clock
+ * @determine_rate: determine the effective rate that can be supported by a
+ *		    clock calculating the closest allowed rate.
+ *		    Note that @rate is an input/output parameter used both to
+ *		    describe the requested rate and report the closest match
+ * @all_rates_get: get the list of all available rates for the specified clock.
  * @enable: enables the specified clock
  * @disable: disables the specified clock
  * @state_get: get the status of the specified clock
@@ -108,6 +108,10 @@ struct scmi_clk_proto_ops {
 			u64 *rate);
 	int (*rate_set)(const struct scmi_protocol_handle *ph, u32 clk_id,
 			u64 rate);
+	int (*determine_rate)(const struct scmi_protocol_handle *ph, u32 clk_id,
+			      unsigned long *rate);
+	const struct scmi_clock_rates __must_check *(*all_rates_get)
+		(const struct scmi_protocol_handle *ph, u32 clk_id);
 	int (*enable)(const struct scmi_protocol_handle *ph, u32 clk_id,
 		      bool atomic);
 	int (*disable)(const struct scmi_protocol_handle *ph, u32 clk_id,
@@ -901,7 +905,7 @@ struct scmi_notify_ops {
  */
 struct scmi_handle {
 	struct device *dev;
-	struct scmi_revision_info *version;
+	struct scmi_base_info *version;
 
 	int __must_check (*devm_protocol_acquire)(struct scmi_device *sdev,
 						  u8 proto);
diff --git a/include/linux/soc/mediatek/mtk-cmdq.h b/include/linux/soc/mediatek/mtk-cmdq.h
index a06b5a61f337..03bb85462566 100644
--- a/include/linux/soc/mediatek/mtk-cmdq.h
+++ b/include/linux/soc/mediatek/mtk-cmdq.h
@@ -446,6 +446,24 @@ static inline int cmdq_pkt_jump(struct cmdq_pkt *pkt, dma_addr_t addr, u8 shift_
 int cmdq_pkt_jump_rel(struct cmdq_pkt *pkt, s32 offset, u8 shift_pa);
 
 /**
+ * cmdq_pkt_jump_rel_temp() - Temporary wrapper for new CMDQ helper API
+ * @pkt:	the CMDQ packet
+ * @offset:	relative offset of target instruction buffer from current PC.
+ * @shift_pa:	[DEPRECATED] shift bits of physical address in CMDQ instruction.
+ *		This value is got by cmdq_get_shift_pa().
+ *
+ * This function is a temporary wrapper that was introduced only for ease of
+ * migration of the many users of the CMDQ API located in multiple kernel
+ * subsystems.
+ *
+ * This has to be removed after all users are migrated to the newer CMDQ API.
+ */
+static inline int cmdq_pkt_jump_rel_temp(struct cmdq_pkt *pkt, s32 offset, u8 shift_pa)
+{
+	return cmdq_pkt_jump_rel(pkt, offset, shift_pa);
+}
+
+/**
  * cmdq_pkt_eoc() - Append EOC and ask GCE to generate an IRQ at end of execution
  * @pkt:	The CMDQ packet
  *
@@ -599,6 +617,12 @@ static inline int cmdq_pkt_jump_rel(struct cmdq_pkt *pkt, s32 offset, u8 shift_p
 	return -EINVAL;
 }
 
+/* This wrapper has to be removed after all users migrated to jump_rel */
+static inline int cmdq_pkt_jump_rel_temp(struct cmdq_pkt *pkt, s32 offset, u8 shift_pa)
+{
+	return -EINVAL;
+}
+
 static inline int cmdq_pkt_eoc(struct cmdq_pkt *pkt)
 {
 	return -EINVAL;
diff --git a/include/linux/soc/qcom/geni-se.h b/include/linux/soc/qcom/geni-se.h
index 0a984e2579fe..c5e6ab85df09 100644
--- a/include/linux/soc/qcom/geni-se.h
+++ b/include/linux/soc/qcom/geni-se.h
@@ -60,18 +60,24 @@ struct geni_icc_path {
  * @dev:		Pointer to the Serial Engine device
  * @wrapper:		Pointer to the parent QUP Wrapper core
  * @clk:		Handle to the core serial engine clock
+ * @core_clk:		Auxiliary clock, which may be required by a protocol
  * @num_clk_levels:	Number of valid clock levels in clk_perf_tbl
  * @clk_perf_tbl:	Table of clock frequency input to serial engine clock
  * @icc_paths:		Array of ICC paths for SE
+ * @pd_list:		Power domain list for managing power domains
+ * @has_opp:		Indicates if OPP is supported
  */
 struct geni_se {
 	void __iomem *base;
 	struct device *dev;
 	struct geni_wrapper *wrapper;
 	struct clk *clk;
+	struct clk *core_clk;
 	unsigned int num_clk_levels;
 	unsigned long *clk_perf_tbl;
 	struct geni_icc_path icc_paths[3];
+	struct dev_pm_domain_list *pd_list;
+	bool has_opp;
 };
 
 /* Common SE registers */
@@ -528,12 +534,25 @@ void geni_se_rx_dma_unprep(struct geni_se *se, dma_addr_t iova, size_t len);
 int geni_icc_get(struct geni_se *se, const char *icc_ddr);
 
 int geni_icc_set_bw(struct geni_se *se);
+int geni_icc_set_bw_ab(struct geni_se *se, u32 core_ab, u32 cfg_ab, u32 ddr_ab);
 void geni_icc_set_tag(struct geni_se *se, u32 tag);
 
 int geni_icc_enable(struct geni_se *se);
 
 int geni_icc_disable(struct geni_se *se);
 
+int geni_se_resources_init(struct geni_se *se);
+
+int geni_se_resources_activate(struct geni_se *se);
+
+int geni_se_resources_deactivate(struct geni_se *se);
+
 int geni_load_se_firmware(struct geni_se *se, enum geni_se_protocol_type protocol);
+
+int geni_se_domain_attach(struct geni_se *se);
+
+int geni_se_set_perf_level(struct geni_se *se, unsigned long level);
+
+int geni_se_set_perf_opp(struct geni_se *se, unsigned long clk_freq);
 #endif
 #endif
diff --git a/include/linux/soc/qcom/llcc-qcom.h b/include/linux/soc/qcom/llcc-qcom.h
index 227125d84318..f3ed63e475ab 100644
--- a/include/linux/soc/qcom/llcc-qcom.h
+++ b/include/linux/soc/qcom/llcc-qcom.h
@@ -89,18 +89,20 @@
 
 /**
  * struct llcc_slice_desc - Cache slice descriptor
- * @slice_id: llcc slice id
- * @slice_size: Size allocated for the llcc slice
+ * @slice_id: LLCC slice id
+ * @uid: Unique ID associated with the LLCC device
+ * @slice_size: Size allocated for the LLCC slice
  * @refcount: Atomic counter to track activate/deactivate calls
  */
 struct llcc_slice_desc {
 	u32 slice_id;
+	u32 uid;
 	size_t slice_size;
 	refcount_t refcount;
 };
 
 /**
- * struct llcc_edac_reg_data - llcc edac registers data for each error type
+ * struct llcc_edac_reg_data - LLCC EDAC registers data for each error type
  * @name: Name of the error
  * @reg_cnt: Number of registers
  * @count_mask: Mask value to get the error count
@@ -146,21 +148,23 @@ struct llcc_edac_reg_offset {
 };
 
 /**
- * struct llcc_drv_data - Data associated with the llcc driver
- * @regmaps: regmaps associated with the llcc device
- * @bcast_regmap: regmap associated with llcc broadcast OR offset
- * @bcast_and_regmap: regmap associated with llcc broadcast AND offset
+ * struct llcc_drv_data - Data associated with the LLCC driver
+ * @dev: device back-pointer for this LLCC instance
+ * @regmaps: regmaps associated with the LLCC device
+ * @bcast_regmap: regmap associated with LLCC broadcast OR offset
+ * @bcast_and_regmap: regmap associated with LLCC broadcast AND offset
  * @cfg: pointer to the data structure for slice configuration
  * @edac_reg_offset: Offset of the LLCC EDAC registers
  * @lock: mutex associated with each slice
  * @cfg_size: size of the config data table
- * @num_banks: Number of llcc banks
- * @ecc_irq: interrupt for llcc cache error detection and reporting
+ * @num_banks: Number of LLCC banks
+ * @ecc_irq: interrupt for LLCC cache error detection and reporting
  * @ecc_irq_configured: 'True' if firmware has already configured the irq propagation
- * @desc: Array pointer of pre-allocated LLCC slice descriptors
  * @version: Indicates the LLCC version
+ * @desc: Array pointer of pre-allocated LLCC slice descriptors
  */
 struct llcc_drv_data {
+	struct device *dev;
 	struct regmap **regmaps;
 	struct regmap *bcast_regmap;
 	struct regmap *bcast_and_regmap;
@@ -177,38 +181,38 @@ struct llcc_drv_data {
 
 #if IS_ENABLED(CONFIG_QCOM_LLCC)
 /**
- * llcc_slice_getd - get llcc slice descriptor
+ * llcc_slice_getd - get LLCC slice descriptor
  * @uid: usecase_id of the client
  */
 struct llcc_slice_desc *llcc_slice_getd(u32 uid);
 
 /**
- * llcc_slice_putd - llcc slice descritpor
- * @desc: Pointer to llcc slice descriptor
+ * llcc_slice_putd - LLCC slice descriptor
+ * @desc: Pointer to LLCC slice descriptor
  */
 void llcc_slice_putd(struct llcc_slice_desc *desc);
 
 /**
  * llcc_get_slice_id - get slice id
- * @desc: Pointer to llcc slice descriptor
+ * @desc: Pointer to LLCC slice descriptor
  */
 int llcc_get_slice_id(struct llcc_slice_desc *desc);
 
 /**
- * llcc_get_slice_size - llcc slice size
- * @desc: Pointer to llcc slice descriptor
+ * llcc_get_slice_size - LLCC slice size
+ * @desc: Pointer to LLCC slice descriptor
  */
 size_t llcc_get_slice_size(struct llcc_slice_desc *desc);
 
 /**
- * llcc_slice_activate - Activate the llcc slice
- * @desc: Pointer to llcc slice descriptor
+ * llcc_slice_activate - Activate the LLCC slice
+ * @desc: Pointer to LLCC slice descriptor
  */
 int llcc_slice_activate(struct llcc_slice_desc *desc);
 
 /**
- * llcc_slice_deactivate - Deactivate the llcc slice
- * @desc: Pointer to llcc slice descriptor
+ * llcc_slice_deactivate - Deactivate the LLCC slice
+ * @desc: Pointer to LLCC slice descriptor
  */
 int llcc_slice_deactivate(struct llcc_slice_desc *desc);
 
diff --git a/include/linux/soc/ti/knav_dma.h b/include/linux/soc/ti/knav_dma.h
index 18d806a8e52c..eb1e6b014eaf 100644
--- a/include/linux/soc/ti/knav_dma.h
+++ b/include/linux/soc/ti/knav_dma.h
@@ -75,7 +75,7 @@ enum knav_dma_desc_type {
  * struct knav_dma_tx_cfg:	Tx channel configuration
  * @filt_einfo:			Filter extended packet info
  * @filt_pswords:		Filter PS words present
- * @knav_dma_tx_priority:	Tx channel scheduling priority
+ * @priority:			Tx channel scheduling priority
  */
 struct knav_dma_tx_cfg {
 	bool				filt_einfo;
@@ -87,13 +87,13 @@ struct knav_dma_tx_cfg {
  * struct knav_dma_rx_cfg:	Rx flow configuration
  * @einfo_present:		Extended packet info present
  * @psinfo_present:		PS words present
- * @knav_dma_rx_err_mode:	Error during buffer starvation
- * @knav_dma_desc_type:	Host or Monolithic desc
+ * @err_mode:			Error during buffer starvation
+ * @desc_type:			Host or Monolithic desc
  * @psinfo_at_sop:		PS word located at start of packet
  * @sop_offset:			Start of packet offset
  * @dst_q:			Destination queue for a given flow
  * @thresh:			Rx flow size threshold
- * @fdq[]:			Free desc Queue array
+ * @fdq:			Free desc Queue array
  * @sz_thresh0:			RX packet size threshold 0
  * @sz_thresh1:			RX packet size threshold 1
  * @sz_thresh2:			RX packet size threshold 2
@@ -115,7 +115,8 @@ struct knav_dma_rx_cfg {
 
 /**
  * struct knav_dma_cfg:	Pktdma channel configuration
- * @sl_cfg:			Slave configuration
+ * @direction:			DMA transfer mode and direction
+ * @u:				union containing @tx or @rx
  * @tx:				Tx channel configuration
  * @rx:				Rx flow configuration
  */
diff --git a/include/soc/qcom/qcom-spmi-pmic.h b/include/soc/qcom/qcom-spmi-pmic.h
index 2cf9e2d8cd55..997fa18d70fe 100644
--- a/include/soc/qcom/qcom-spmi-pmic.h
+++ b/include/soc/qcom/qcom-spmi-pmic.h
@@ -50,9 +50,22 @@
 #define PMR735B_SUBTYPE		0x34
 #define PM6350_SUBTYPE		0x36
 #define PM4125_SUBTYPE		0x37
+#define PM8010_SUBTYPE		0x41
+#define PM8550VS_SUBTYPE	0x45
+#define PM8550VE_SUBTYPE	0x46
+#define PMR735D_SUBTYPE	0x48
+#define PM8550_SUBTYPE		0x49
+#define PMK8550_SUBTYPE	0x4a
 #define PMM8650AU_SUBTYPE       0x4e
 #define PMM8650AU_PSAIL_SUBTYPE 0x4f
-
+#define PM8750B_SUBTYPE	0x56
+#define PMD8028_SUBTYPE	0x57
+#define PMK8850_SUBTYPE	0x5c
+#define PMH0101_SUBTYPE	0x5d
+#define SMB2370_SUBTYPE	0x5f
+#define PMH0104_SUBTYPE	0x60
+#define PMH0110_SUBTYPE	0x61
+#define PMCX0102_SUBTYPE	0x62
 #define PMI8998_FAB_ID_SMIC	0x11
 #define PMI8998_FAB_ID_GF	0x30
 
diff --git a/include/soc/tegra/mc.h b/include/soc/tegra/mc.h
index e6da035d1306..25d465d70493 100644
--- a/include/soc/tegra/mc.h
+++ b/include/soc/tegra/mc.h
@@ -164,7 +164,7 @@ struct tegra_mc_ops {
 	 */
 	int (*probe)(struct tegra_mc *mc);
 	void (*remove)(struct tegra_mc *mc);
-	int (*resume)(struct tegra_mc *mc);
+	void (*resume)(struct tegra_mc *mc);
 	int (*probe_device)(struct tegra_mc *mc, struct device *dev);
 };
 
diff --git a/include/soc/tegra/pmc.h b/include/soc/tegra/pmc.h
index 1fd21be02577..4bcbf19d75ac 100644
--- a/include/soc/tegra/pmc.h
+++ b/include/soc/tegra/pmc.h
@@ -18,10 +18,6 @@ struct clk;
 struct reset_control;
 struct tegra_pmc;
 
-bool tegra_pmc_cpu_is_powered(unsigned int cpuid);
-int tegra_pmc_cpu_power_on(unsigned int cpuid);
-int tegra_pmc_cpu_remove_clamping(unsigned int cpuid);
-
 /*
  * powergate and I/O rail APIs
  */
@@ -163,22 +159,6 @@ int tegra_pmc_powergate_sequence_power_up(struct tegra_pmc *pmc,
 int tegra_pmc_io_pad_power_enable(struct tegra_pmc *pmc, enum tegra_io_pad id);
 int tegra_pmc_io_pad_power_disable(struct tegra_pmc *pmc, enum tegra_io_pad id);
 
-/* legacy */
-int tegra_powergate_power_on(unsigned int id);
-int tegra_powergate_power_off(unsigned int id);
-int tegra_powergate_remove_clamping(unsigned int id);
-
-int tegra_powergate_sequence_power_up(unsigned int id, struct clk *clk,
-				      struct reset_control *rst);
-
-int tegra_io_pad_power_enable(enum tegra_io_pad id);
-int tegra_io_pad_power_disable(enum tegra_io_pad id);
-
-void tegra_pmc_set_suspend_mode(enum tegra_suspend_mode mode);
-void tegra_pmc_enter_suspend_mode(enum tegra_suspend_mode mode);
-
-bool tegra_pmc_core_domain_state_synced(void);
-
 #else
 static inline struct tegra_pmc *devm_tegra_pmc_get(struct device *dev)
 {
@@ -223,42 +203,23 @@ tegra_pmc_io_pad_power_disable(struct tegra_pmc *pmc, enum tegra_io_pad id)
 {
 	return -ENOSYS;
 }
+#endif /* CONFIG_SOC_TEGRA_PMC */
 
-static inline int tegra_powergate_power_on(unsigned int id)
-{
-	return -ENOSYS;
-}
-
-static inline int tegra_powergate_power_off(unsigned int id)
-{
-	return -ENOSYS;
-}
-
-static inline int tegra_powergate_remove_clamping(unsigned int id)
-{
-	return -ENOSYS;
-}
-
-static inline int tegra_powergate_sequence_power_up(unsigned int id,
-						    struct clk *clk,
-						    struct reset_control *rst)
-{
-	return -ENOSYS;
-}
-
-static inline int tegra_io_pad_power_enable(enum tegra_io_pad id)
-{
-	return -ENOSYS;
-}
-
-static inline int tegra_io_pad_power_disable(enum tegra_io_pad id)
-{
-	return -ENOSYS;
-}
+/* 32-bit ARM platforms only */
+#if defined(CONFIG_ARM)
+bool tegra_pmc_cpu_is_powered(unsigned int cpuid);
+int tegra_pmc_cpu_power_on(unsigned int cpuid);
+int tegra_pmc_cpu_remove_clamping(unsigned int cpuid);
+bool tegra_pmc_core_domain_state_synced(void);
 
-static inline int tegra_io_pad_get_voltage(enum tegra_io_pad id)
+#if defined(CONFIG_SOC_TEGRA_PMC) && defined(CONFIG_PM_SLEEP)
+enum tegra_suspend_mode tegra_pmc_get_suspend_mode(void);
+void tegra_pmc_set_suspend_mode(enum tegra_suspend_mode mode);
+void tegra_pmc_enter_suspend_mode(enum tegra_suspend_mode mode);
+#else
+static inline enum tegra_suspend_mode tegra_pmc_get_suspend_mode(void)
 {
-	return -ENOSYS;
+	return TEGRA_SUSPEND_NONE;
 }
 
 static inline void tegra_pmc_set_suspend_mode(enum tegra_suspend_mode mode)
@@ -268,21 +229,13 @@ static inline void tegra_pmc_set_suspend_mode(enum tegra_suspend_mode mode)
 static inline void tegra_pmc_enter_suspend_mode(enum tegra_suspend_mode mode)
 {
 }
-
+#endif
+#else
+/* needed for COMPILE_TEST */
 static inline bool tegra_pmc_core_domain_state_synced(void)
 {
 	return false;
 }
-
-#endif /* CONFIG_SOC_TEGRA_PMC */
-
-#if defined(CONFIG_SOC_TEGRA_PMC) && defined(CONFIG_PM_SLEEP)
-enum tegra_suspend_mode tegra_pmc_get_suspend_mode(void);
-#else
-static inline enum tegra_suspend_mode tegra_pmc_get_suspend_mode(void)
-{
-	return TEGRA_SUSPEND_NONE;
-}
 #endif
 
 #endif /* __SOC_TEGRA_PMC_H__ */
diff --git a/include/uapi/linux/fsl_hypervisor.h b/include/uapi/linux/fsl_hypervisor.h
index 1e237fba951f..ab4388441e80 100644
--- a/include/uapi/linux/fsl_hypervisor.h
+++ b/include/uapi/linux/fsl_hypervisor.h
@@ -114,9 +114,9 @@ struct fsl_hv_ioctl_stop {
  * @target: the partition ID of the target partition, or -1 for this
  *          partition
  * @reserved: reserved, must be set to 0
- * @local_addr: user-space virtual address of a buffer in the local
+ * @local_vaddr: user-space virtual address of a buffer in the local
  *              partition
- * @remote_addr: guest physical address of a buffer in the
+ * @remote_paddr: guest physical address of a buffer in the
  *           remote partition
  * @count: the number of bytes to copy.  Both the local and remote
  *         buffers must be at least 'count' bytes long