diff options
| author | Daniel Machon <daniel.machon@microchip.com> | 2026-02-10 16:44:01 +0300 |
|---|---|---|
| committer | Jakub Kicinski <kuba@kernel.org> | 2026-02-13 05:59:27 +0300 |
| commit | 6c28aa8dfdf24f554d4c5d4ff7d723a95360d94a (patch) | |
| tree | 455bd334c36df551275a6d61008b16e386cb43fd /include | |
| parent | 8930878101cd40063888a68af73b1b0f8b6c79bc (diff) | |
| download | linux-6c28aa8dfdf24f554d4c5d4ff7d723a95360d94a.tar.xz | |
net: sparx5/lan969x: fix DWRR cost max to match hardware register width
DWRR (Deficit Weighted Round Robin) scheduling distributes bandwidth
across traffic classes based on per-queue cost values, where lower cost
means higher bandwidth share.
The SPX5_DWRR_COST_MAX constant is 63 (6 bits) but the hardware
register field HSCH_DWRR_ENTRY_DWRR_COST is GENMASK(24, 20), only
5 bits wide (max 31). This causes sparx5_weight_to_hw_cost() to
compute cost values that silently overflow via FIELD_PREP, resulting
in incorrect scheduling weights.
Set SPX5_DWRR_COST_MAX to 31 to match the hardware register width.
Fixes: 211225428d65 ("net: microchip: sparx5: add support for offloading ets qdisc")
Signed-off-by: Daniel Machon <daniel.machon@microchip.com>
Reviewed-by: Simon Horman <horms@kernel.org>
Link: https://patch.msgid.link/20260210-sparx5-fix-dwrr-cost-max-v1-1-58fbdbc25652@microchip.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
Diffstat (limited to 'include')
0 files changed, 0 insertions, 0 deletions