diff options
| author | Robert Richter <robert.richter@amd.com> | 2008-06-12 22:19:23 +0400 |
|---|---|---|
| committer | Ingo Molnar <mingo@elte.hu> | 2008-07-08 09:47:39 +0400 |
| commit | 3a27dd1ce5de08e21e0266ddf00e6f1f843bfe8b (patch) | |
| tree | b72316cfbe10d1f955a0cb9553879fb2bb14344b /include | |
| parent | 24bfdca7b7da971ef9a483303a096ac6d4b3a02c (diff) | |
| download | linux-3a27dd1ce5de08e21e0266ddf00e6f1f843bfe8b.tar.xz | |
x86: Move PCI IO ECS code to x86/pci
"Form follows function". Code is now where it belongs to.
Signed-off-by: Robert Richter <robert.richter@amd.com>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'include')
| -rw-r--r-- | include/asm-x86/cpufeature.h | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/include/asm-x86/cpufeature.h b/include/asm-x86/cpufeature.h index 40fcbba00f15..0d609c837a41 100644 --- a/include/asm-x86/cpufeature.h +++ b/include/asm-x86/cpufeature.h @@ -79,7 +79,6 @@ #define X86_FEATURE_REP_GOOD (3*32+16) /* rep microcode works well on this CPU */ #define X86_FEATURE_MFENCE_RDTSC (3*32+17) /* Mfence synchronizes RDTSC */ #define X86_FEATURE_LFENCE_RDTSC (3*32+18) /* Lfence synchronizes RDTSC */ -#define X86_FEATURE_PCI_EXT_CFG (3*32+19) /* PCI extended cfg access */ /* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */ #define X86_FEATURE_XMM3 (4*32+ 0) /* Streaming SIMD Extensions-3 */ @@ -188,7 +187,6 @@ extern const char * const x86_power_flags[32]; #define cpu_has_gbpages boot_cpu_has(X86_FEATURE_GBPAGES) #define cpu_has_arch_perfmon boot_cpu_has(X86_FEATURE_ARCH_PERFMON) #define cpu_has_pat boot_cpu_has(X86_FEATURE_PAT) -#define cpu_has_pci_ext_cfg boot_cpu_has(X86_FEATURE_PCI_EXT_CFG) #if defined(CONFIG_X86_INVLPG) || defined(CONFIG_X86_64) # define cpu_has_invlpg 1 |