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| author | Arnd Bergmann <arnd@arndb.de> | 2016-07-14 18:26:36 +0300 |
|---|---|---|
| committer | Arnd Bergmann <arnd@arndb.de> | 2016-07-14 18:26:36 +0300 |
| commit | 17ef34e9dcd8bbf80a5b097df72bd61d20fe6900 (patch) | |
| tree | b8e9f2abcbc204630d50ee74e113eb3e9a69c47c /include | |
| parent | 8ebe624ab3e3e1a1bd63a8912bdaa4924a59a87a (diff) | |
| parent | e0c98b9171eecf1745eda08de86081db8ec41d51 (diff) | |
| download | linux-17ef34e9dcd8bbf80a5b097df72bd61d20fe6900.tar.xz | |
Merge branch 'renesas/rcar-sysc' into next/dt64
This is needed to work around another failure with "make dtbs":
In file included from ../arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts:12:0:
arch/arm64/boot/dts/renesas/r8a7796.dtsi:13:44: fatal error: dt-bindings/power/r8a7796-sysc.h: No such file or directory
* renesas/rcar-sysc:
soc: renesas: rcar-sysc: Add support for R-Car M3-W power areas
soc: renesas: Add r8a7796 SYSC PM Domain Binding Definitions
soc: renesas: rcar-sysc: Document r8a7796 support
Diffstat (limited to 'include')
| -rw-r--r-- | include/dt-bindings/power/r8a7796-sysc.h | 36 |
1 files changed, 36 insertions, 0 deletions
diff --git a/include/dt-bindings/power/r8a7796-sysc.h b/include/dt-bindings/power/r8a7796-sysc.h new file mode 100644 index 000000000000..5b4daab44daa --- /dev/null +++ b/include/dt-bindings/power/r8a7796-sysc.h @@ -0,0 +1,36 @@ +/* + * Copyright (C) 2016 Glider bvba + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + */ +#ifndef __DT_BINDINGS_POWER_R8A7796_SYSC_H__ +#define __DT_BINDINGS_POWER_R8A7796_SYSC_H__ + +/* + * These power domain indices match the numbers of the interrupt bits + * representing the power areas in the various Interrupt Registers + * (e.g. SYSCISR, Interrupt Status Register) + */ + +#define R8A7796_PD_CA57_CPU0 0 +#define R8A7796_PD_CA57_CPU1 1 +#define R8A7796_PD_CA53_CPU0 5 +#define R8A7796_PD_CA53_CPU1 6 +#define R8A7796_PD_CA53_CPU2 7 +#define R8A7796_PD_CA53_CPU3 8 +#define R8A7796_PD_CA57_SCU 12 +#define R8A7796_PD_CR7 13 +#define R8A7796_PD_A3VC 14 +#define R8A7796_PD_3DG_A 17 +#define R8A7796_PD_3DG_B 18 +#define R8A7796_PD_CA53_SCU 21 +#define R8A7796_PD_A3IR 24 +#define R8A7796_PD_A2VC0 25 +#define R8A7796_PD_A2VC1 26 + +/* Always-on power area */ +#define R8A7796_PD_ALWAYS_ON 32 + +#endif /* __DT_BINDINGS_POWER_R8A7796_SYSC_H__ */ |