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| author | Jakub Kicinski <kuba@kernel.org> | 2025-07-11 04:13:52 +0300 |
|---|---|---|
| committer | Jakub Kicinski <kuba@kernel.org> | 2025-07-11 04:13:52 +0300 |
| commit | 0106424ae408e1ddc32bfc4f5f9f3d009ee7343f (patch) | |
| tree | 88d4ad4af1bb1f2ab96385dc8e10989c07b89101 /include | |
| parent | 380a8891fdcb4e81bc30074c497e6892a827eb2a (diff) | |
| parent | af350ee72e9dda474af4697ff59601cb73387b31 (diff) | |
| download | linux-0106424ae408e1ddc32bfc4f5f9f3d009ee7343f.tar.xz | |
Merge branch 'net-ftgmac100-add-soc-reset-support-for-rmii-mode'
Jacky Chou says:
====================
net: ftgmac100: Add SoC reset support for RMII mode
This patch series adds support for an optional reset line to the
ftgmac100 ethernet controller, as used on Aspeed SoCs. On these SoCs,
the internal MAC reset is not sufficient to reset the RMII interface.
By providing a SoC-level reset via the device tree "resets" property,
the driver can properly reset both the MAC and RMII logic, ensuring
correct operation in RMII mode.
The series includes:
- Device tree binding update to document the new "resets" property.
- Addition of MAC1/2/3/4 reset definitions for AST2600.
- Driver changes to assert/deassert the reset line as needed.
This improves reliability and initialization of the MAC in RMII mode
on Aspeed platforms.
====================
Link: https://patch.msgid.link/20250709070809.2560688-1-jacky_chou@aspeedtech.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
Diffstat (limited to 'include')
| -rw-r--r-- | include/dt-bindings/clock/ast2600-clock.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/include/dt-bindings/clock/ast2600-clock.h b/include/dt-bindings/clock/ast2600-clock.h index 7ae96c7bd72f..f60fff261130 100644 --- a/include/dt-bindings/clock/ast2600-clock.h +++ b/include/dt-bindings/clock/ast2600-clock.h @@ -122,6 +122,8 @@ #define ASPEED_RESET_PCIE_DEV_OEN 20 #define ASPEED_RESET_PCIE_RC_O 19 #define ASPEED_RESET_PCIE_RC_OEN 18 +#define ASPEED_RESET_MAC2 12 +#define ASPEED_RESET_MAC1 11 #define ASPEED_RESET_PCI_DP 5 #define ASPEED_RESET_HACE 4 #define ASPEED_RESET_AHB 1 |
