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author | Bjorn Helgaas <bhelgaas@google.com> | 2024-09-19 22:25:26 +0300 |
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committer | Bjorn Helgaas <bhelgaas@google.com> | 2024-09-19 22:25:26 +0300 |
commit | 9d4f1c0747e2937c830d135a460d727002caed3d (patch) | |
tree | d7b5634e79a228a73b7c3356c215943310683282 /include/uapi | |
parent | e642aa6b38762a2af3a7e0c5e6dac5841c15dea0 (diff) | |
parent | 759ec28242894f2006a1606c1d6e9aca48cecfcf (diff) | |
download | linux-9d4f1c0747e2937c830d135a460d727002caed3d.tar.xz |
Merge branch 'pci/npem'
- Initialize leds class earlier (with an unfortunate Makefile ordering
change) so the PCI NPEM driver can use it (Mariusz Tkaczyk)
- Add Native PCIe Enclosure Management (NPEM) support for sysfs control of
NVMe RAID storage indicators (ok/fail/locate/rebuild/etc) (Mariusz
Tkaczyk)
- Add support for the ACPI _DSM PCIe SSD status LED management, which is
functionally similar to NPEM but mediated by platform firmware (Mariusz
Tkaczyk)
* pci/npem:
PCI/NPEM: Add _DSM PCIe SSD status LED management
PCI/NPEM: Add Native PCIe Enclosure Management support
leds: Init leds class earlier
Diffstat (limited to 'include/uapi')
-rw-r--r-- | include/uapi/linux/pci_regs.h | 35 |
1 files changed, 35 insertions, 0 deletions
diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h index f94591f9f5e9..12323b3334a9 100644 --- a/include/uapi/linux/pci_regs.h +++ b/include/uapi/linux/pci_regs.h @@ -742,6 +742,7 @@ #define PCI_EXT_CAP_ID_DVSEC 0x23 /* Designated Vendor-Specific */ #define PCI_EXT_CAP_ID_DLF 0x25 /* Data Link Feature */ #define PCI_EXT_CAP_ID_PL_16GT 0x26 /* Physical Layer 16.0 GT/s */ +#define PCI_EXT_CAP_ID_NPEM 0x29 /* Native PCIe Enclosure Management */ #define PCI_EXT_CAP_ID_PL_32GT 0x2A /* Physical Layer 32.0 GT/s */ #define PCI_EXT_CAP_ID_DOE 0x2E /* Data Object Exchange */ #define PCI_EXT_CAP_ID_MAX PCI_EXT_CAP_ID_DOE @@ -1123,6 +1124,40 @@ #define PCI_PL_16GT_LE_CTRL_USP_TX_PRESET_MASK 0x000000F0 #define PCI_PL_16GT_LE_CTRL_USP_TX_PRESET_SHIFT 4 +/* Native PCIe Enclosure Management */ +#define PCI_NPEM_CAP 0x04 /* NPEM capability register */ +#define PCI_NPEM_CAP_CAPABLE 0x00000001 /* NPEM Capable */ + +#define PCI_NPEM_CTRL 0x08 /* NPEM control register */ +#define PCI_NPEM_CTRL_ENABLE 0x00000001 /* NPEM Enable */ + +/* + * Native PCIe Enclosure Management indication bits and Reset command bit + * are corresponding for capability and control registers. + */ +#define PCI_NPEM_CMD_RESET 0x00000002 /* Reset Command */ +#define PCI_NPEM_IND_OK 0x00000004 /* OK */ +#define PCI_NPEM_IND_LOCATE 0x00000008 /* Locate */ +#define PCI_NPEM_IND_FAIL 0x00000010 /* Fail */ +#define PCI_NPEM_IND_REBUILD 0x00000020 /* Rebuild */ +#define PCI_NPEM_IND_PFA 0x00000040 /* Predicted Failure Analysis */ +#define PCI_NPEM_IND_HOTSPARE 0x00000080 /* Hot Spare */ +#define PCI_NPEM_IND_ICA 0x00000100 /* In Critical Array */ +#define PCI_NPEM_IND_IFA 0x00000200 /* In Failed Array */ +#define PCI_NPEM_IND_IDT 0x00000400 /* Device Type */ +#define PCI_NPEM_IND_DISABLED 0x00000800 /* Disabled */ +#define PCI_NPEM_IND_SPEC_0 0x01000000 +#define PCI_NPEM_IND_SPEC_1 0x02000000 +#define PCI_NPEM_IND_SPEC_2 0x04000000 +#define PCI_NPEM_IND_SPEC_3 0x08000000 +#define PCI_NPEM_IND_SPEC_4 0x10000000 +#define PCI_NPEM_IND_SPEC_5 0x20000000 +#define PCI_NPEM_IND_SPEC_6 0x40000000 +#define PCI_NPEM_IND_SPEC_7 0x80000000 + +#define PCI_NPEM_STATUS 0x0c /* NPEM status register */ +#define PCI_NPEM_STATUS_CC 0x00000001 /* Command Completed */ + /* Data Object Exchange */ #define PCI_DOE_CAP 0x04 /* DOE Capabilities Register */ #define PCI_DOE_CAP_INT_SUP 0x00000001 /* Interrupt Support */ |