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| author | Sascha Bischoff <Sascha.Bischoff@arm.com> | 2026-01-28 21:00:06 +0300 |
|---|---|---|
| committer | Marc Zyngier <maz@kernel.org> | 2026-01-30 14:10:46 +0300 |
| commit | b583177aafe3ca753ddd3624c8731a93d0cd0b37 (patch) | |
| tree | 877eeea2b08e497e68cd1926394ab57e8201c3fb /include/uapi/linux | |
| parent | 4a03431b742b4edc24fe1a14d355de1df6d80f86 (diff) | |
| download | linux-b583177aafe3ca753ddd3624c8731a93d0cd0b37.tar.xz | |
arm64/sysreg: Drop ICH_HFGRTR_EL2.ICC_HAPR_EL1 and make RES1
The GICv5 architecture is dropping the ICC_HAPR_EL1 and ICV_HAPR_EL1
system registers. These registers were never added to the sysregs, but
the traps for them were.
Drop the trap bit from the ICH_HFGRTR_EL2 and make it Res1 as per the
upcoming GICv5 spec change. Additionally, update the EL2 setup code to
not attempt to set that bit.
Signed-off-by: Sascha Bischoff <sascha.bischoff@arm.com>
Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>
Link: https://patch.msgid.link/20260128175919.3828384-4-sascha.bischoff@arm.com
Signed-off-by: Marc Zyngier <maz@kernel.org>
Diffstat (limited to 'include/uapi/linux')
0 files changed, 0 insertions, 0 deletions