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| author | Russell King (Oracle) <rmk+kernel@armlinux.org.uk> | 2026-03-05 13:42:26 +0300 |
|---|---|---|
| committer | Jakub Kicinski <kuba@kernel.org> | 2026-03-07 02:39:09 +0300 |
| commit | 4c7e0e081889be876e2d9ee23332c75b6207d5eb (patch) | |
| tree | 98647e1915e1988d584ff1dd8197427a12c35254 /include/uapi/linux | |
| parent | 507ccb668f2db1377defdc54068eab3398bd5974 (diff) | |
| download | linux-4c7e0e081889be876e2d9ee23332c75b6207d5eb.tar.xz | |
net: stmmac: mdio: convert MDC clock divisor selection to tables
Convert the MDC clock divisor selection to tabular format.
Note that there is a change for 300MHz, but this is not a problem,
as the MDC clock remains within the useable ranges, which are:
STMMAC_CSR_500_800M /324 1.54 - 2.47MHz
STMMAC_CSR_300_500M /204 1.47 - 2.45MHz
STMMAC_CSR_250_300M /124 2.02 - 2.42MHz
STMMAC_CSR_150_250M /102 1.47 - 2.45MHz
STMMAC_CSR_100_150M /62 1.61 - 2.42MHz
STMMAC_CSR_60_100M /42 1.43 - 2.38MHz
STMMAC_CSR_35_60M /26 1.35 - 2.31MHz
STMMAC_CSR_20_35M /16 1.25 - 2.19MHz
Thus, with the change of divisor for exactly 300MHz, MDC temporarily
changes from 2.42MHz to 1.47MHz for the sake of consistency.
The databook does not specify whether the frequency limits for the
CSR divider are inclusive or exclusive.
Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
Tested-by: Maxime Chevallier <maxime.chevallier@bootlin.com>
Link: https://patch.msgid.link/E1vy69y-0000000Btwd-3oq7@rmk-PC.armlinux.org.uk
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
Diffstat (limited to 'include/uapi/linux')
0 files changed, 0 insertions, 0 deletions