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| author | Ingo Molnar <mingo@kernel.org> | 2015-02-26 14:24:50 +0300 |
|---|---|---|
| committer | Ingo Molnar <mingo@kernel.org> | 2015-02-26 14:24:50 +0300 |
| commit | e9e4e44309f866b115d08ab4a54834008c50a8a4 (patch) | |
| tree | ae9f91e682a4d6592ef263f30a4a0b1a862b7987 /include/uapi/linux/serial_core.h | |
| parent | 8a26ce4e544659256349551283414df504889a59 (diff) | |
| parent | c517d838eb7d07bbe9507871fab3931deccff539 (diff) | |
| download | linux-e9e4e44309f866b115d08ab4a54834008c50a8a4.tar.xz | |
Merge tag 'v4.0-rc1' into perf/core, to refresh the tree
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Diffstat (limited to 'include/uapi/linux/serial_core.h')
| -rw-r--r-- | include/uapi/linux/serial_core.h | 12 |
1 files changed, 11 insertions, 1 deletions
diff --git a/include/uapi/linux/serial_core.h b/include/uapi/linux/serial_core.h index c17218094f18..b2122813f18a 100644 --- a/include/uapi/linux/serial_core.h +++ b/include/uapi/linux/serial_core.h @@ -55,7 +55,8 @@ #define PORT_ALTR_16550_F64 27 /* Altera 16550 UART with 64 FIFOs */ #define PORT_ALTR_16550_F128 28 /* Altera 16550 UART with 128 FIFOs */ #define PORT_RT2880 29 /* Ralink RT2880 internal UART */ -#define PORT_MAX_8250 29 /* max port ID */ +#define PORT_16550A_FSL64 30 /* Freescale 16550 UART with 64 FIFOs */ +#define PORT_MAX_8250 30 /* max port ID */ /* * ARM specific type numbers. These are not currently guaranteed @@ -248,4 +249,13 @@ /* MESON */ #define PORT_MESON 109 +/* Conexant Digicolor */ +#define PORT_DIGICOLOR 110 + +/* SPRD SERIAL */ +#define PORT_SPRD 111 + +/* Cris v10 / v32 SoC */ +#define PORT_CRIS 112 + #endif /* _UAPILINUX_SERIAL_CORE_H */ |