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authorThierry Reding <treding@nvidia.com>2021-06-02 19:32:51 +0300
committerKrzysztof Kozlowski <krzysztof.kozlowski@canonical.com>2021-06-03 22:49:40 +0300
commit4f1ac76e5ed9436ff3cd72e308527fd1e90b193a (patch)
treeb088cc04ad067a71bd684ee5bc16b9f3ddb2193b /include/soc/tegra
parenteeafcdea46936d84e2016e7d965f0b79e75ffd9e (diff)
downloadlinux-4f1ac76e5ed9436ff3cd72e308527fd1e90b193a.tar.xz
memory: tegra: Consolidate register fields
Subsequent patches will add more register fields to the tegra_mc_client structure, so consolidate all register field definitions into a common sub-structure for coherency. Signed-off-by: Thierry Reding <treding@nvidia.com> Link: https://lore.kernel.org/r/20210602163302.120041-2-thierry.reding@gmail.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Diffstat (limited to 'include/soc/tegra')
-rw-r--r--include/soc/tegra/mc.h30
1 files changed, 15 insertions, 15 deletions
diff --git a/include/soc/tegra/mc.h b/include/soc/tegra/mc.h
index d2fbe6a8b25b..dd26505464c2 100644
--- a/include/soc/tegra/mc.h
+++ b/include/soc/tegra/mc.h
@@ -17,25 +17,12 @@ struct clk;
struct device;
struct page;
-struct tegra_smmu_enable {
- unsigned int reg;
- unsigned int bit;
-};
-
struct tegra_mc_timing {
unsigned long rate;
u32 *emem_data;
};
-/* latency allowance */
-struct tegra_mc_la {
- unsigned int reg;
- unsigned int shift;
- unsigned int mask;
- unsigned int def;
-};
-
struct tegra_mc_client {
unsigned int id;
const char *name;
@@ -43,8 +30,21 @@ struct tegra_mc_client {
unsigned int fifo_size;
- struct tegra_smmu_enable smmu;
- struct tegra_mc_la la;
+ struct {
+ /* Tegra SMMU enable */
+ struct {
+ unsigned int reg;
+ unsigned int bit;
+ } smmu;
+
+ /* latency allowance */
+ struct {
+ unsigned int reg;
+ unsigned int shift;
+ unsigned int mask;
+ unsigned int def;
+ } la;
+ } regs;
};
struct tegra_smmu_swgroup {