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| author | Olof Johansson <olof@lixom.net> | 2018-12-12 23:56:36 +0300 |
|---|---|---|
| committer | Olof Johansson <olof@lixom.net> | 2018-12-12 23:56:36 +0300 |
| commit | fafda335f81a6e5af64a3452185299c86ec32b5e (patch) | |
| tree | 6a94fd30425681dfd2d8c2a5ebc823e325bb6b60 /include/linux | |
| parent | 2b6464560852f6c2ee2a37230cf29a23f324737c (diff) | |
| parent | a73900b826ce6faded48ee3e41aa890fbeba4068 (diff) | |
| download | linux-fafda335f81a6e5af64a3452185299c86ec32b5e.tar.xz | |
Merge tag 'imx7ulp-dt-4.21' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into next/dt
i.MX7ULP device tree for 4.21:
- It includes the initial device tree for i.MX7ULP SoC and EVK board
support.
* tag 'imx7ulp-dt-4.21' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
ARM: dts: imx: add imx7ulp evk support
ARM: dts: imx: add common imx7ulp dtsi support
dt-bindings: fsl: add imx7ulp pm related components bindings
dt-bindings: fsl: add compatible for imx7ulp evk
clk: imx: add imx7ulp clk driver
clk: imx: implement new clk_hw based APIs
clk: imx: make mux parent strings const
dt-bindings: clock: add imx7ulp clock binding doc
clk: imx: add imx7ulp composite clk support
clk: imx: add pfdv2 support
clk: imx: add pllv4 support
clk: fractional-divider: add CLK_FRAC_DIVIDER_ZERO_BASED flag support
clk: imx: add gatable clock divider support
Signed-off-by: Olof Johansson <olof@lixom.net>
Diffstat (limited to 'include/linux')
| -rw-r--r-- | include/linux/clk-provider.h | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h index 60c51871b04b..fa0bad94f26b 100644 --- a/include/linux/clk-provider.h +++ b/include/linux/clk-provider.h @@ -601,6 +601,12 @@ void clk_hw_unregister_fixed_factor(struct clk_hw *hw); * @lock: register lock * * Clock with adjustable fractional divider affecting its output frequency. + * + * Flags: + * CLK_FRAC_DIVIDER_ZERO_BASED - by default the numerator and denominator + * is the value read from the register. If CLK_FRAC_DIVIDER_ZERO_BASED + * is set then the numerator and denominator are both the value read + * plus one. */ struct clk_fractional_divider { struct clk_hw hw; @@ -620,6 +626,8 @@ struct clk_fractional_divider { #define to_clk_fd(_hw) container_of(_hw, struct clk_fractional_divider, hw) +#define CLK_FRAC_DIVIDER_ZERO_BASED BIT(0) + extern const struct clk_ops clk_fractional_divider_ops; struct clk *clk_register_fractional_divider(struct device *dev, const char *name, const char *parent_name, unsigned long flags, |