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| author | Qiang Yu <qiang.yu@oss.qualcomm.com> | 2025-11-24 13:24:36 +0300 |
|---|---|---|
| committer | Vinod Koul <vkoul@kernel.org> | 2025-12-23 20:41:04 +0300 |
| commit | ecc12453c8b1aabdedcd663b7e0587f372a2a90d (patch) | |
| tree | 6f8e2e423b00a9edd68aa87f740b9d1d0061a4b9 /include/linux | |
| parent | 5359da47e066edb3fcd36c7349726913ee8628f2 (diff) | |
| download | linux-ecc12453c8b1aabdedcd663b7e0587f372a2a90d.tar.xz | |
phy: qcom-qmp: pcs-pcie: Add v8 register offsets
Kaanapali SoC uses QMP phy with version v8 for PCIe Gen3 x2. Add the new
PCS PCIE specific offsets in a dedicated header file.
Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
Link: https://patch.msgid.link/20251124-kaanapali-pcie-phy-v4-3-d04ee9cca83b@oss.qualcomm.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Diffstat (limited to 'include/linux')
0 files changed, 0 insertions, 0 deletions