Merge tag 'iommu-updates-v7.2' of git://git.kernel.org/pub/scm/linux/kernel/git/iommu/linux

Pull iommu updates from Joerg Roedel:
 "Core Code:

   - Fix dma-iommu scatterlist length handling in the P2PDMA path

   - Extend the generic IOMMU page-table code with detailed gather
     support for more precise invalidations

   - Add pending-gather tracking to generic page-table invalidation
     handling

   - Add support for smaller virtual address sizes in the generic AMDv1
     page-table format, including KUnit coverage

   - Fix page-size bitmap calculation for smaller VA configurations

   - Rework Arm io-pgtable allocation/freeing to consistently use the
     iommu-pages API and address-conversion helpers

   - Add PCI ATS infrastructure for devices that require ATS, including
     always-on ATS handling for pre-CXL devices

  AMD IOMMU:

   - Fix several IOTLB invalidation details, including PDE handling,
     flush-all behavior, and command address encoding

   - Honor IVINFO[VASIZE] when deriving address limits

   - Fix premature loop termination in init_iommu_one()

   - Add Hygon family 18h model 4h IOAPIC support

   - Clean up legacy-mode handling, stale comments, dead IVMD
     exclusion-range code, and unused address-size macros

  Arm SMMU / Arm SMMU v3:

   - SMMUv2:
      - Device-tree binding updates for Qualcomm Hawi, Nord and Shikra
        SoCs
      - Constrain the clocks which can be specified for recent Qualcomm
        SoCs
      - Fix broken compatible string for Qualcomm prefetcher
        configuration an add new entry for the Glymur MDSS
      - Ensure SMMU is powered-up when writing context bank for Adreno
        client

   - SMMUv3:
      - Fix off-by-one in queue allocation retry loop
      - Enable hardware update of access/dirty bits from the SMMU
      - Re-jig command construction to use separate inline helpers for
        each command type

  Intel VT-d:

   - Add the PCI segment number to DMA fault messages

   - Improve support for non-PRI mode SVA

   - Ensure atomicity during context entry teardown

   - Fix RB-tree corruption in the probe error path

  RISC-V IOMMU:

   - Add NAPOT range invalidation support

   - Use detailed gather information for invalidation decisions

   - Compute the best stride for single invalidations

   - Advertise Svpbmt support to the generic page-table code

   - Add capability definitions and clean up command macro encoding

  VeriSilicon IOMMU:

   - Add a new VeriSilicon IOMMU driver

   - Add devicetree binding documentation and MAINTAINERS coverage

   - Add the RK3588 VeriSilicon IOMMU node

   - Apply small cleanups and warning fixes in the new driver

  Rockchip IOMMU:

   - Disable the fetch DTE time limit

  Apple DART:

   - Correct a stale CONFIG_PCIE_APPLE macro name in a comment"

* tag 'iommu-updates-v7.2' of git://git.kernel.org/pub/scm/linux/kernel/git/iommu/linux: (66 commits)
  iommu/dma-iommu: Fix wrong scatterlist length assignment in P2PDMA path
  iommu/amd: Control INVALIDATE_IOMMU_PAGES PDE from the gather
  iommu/amd: Make CMD_INV_IOMMU_ALL_PAGES_ADDRESS match the spec
  iommu/amd: Have amd_iommu_domain_flush_pages() use last
  iommu/amd: Pass last in through to build_inv_address()
  iommu/amd: Simplify build_inv_address()
  iommu/apple-dart: correct CONFIG_PCIE_APPLE macro name in comment
  iommu/vt-d: Fix RB-tree corruption in probe error path
  iommu/vt-d: Improve IOMMU fault information
  iommu/vt-d: Remove typo from pasid_pte_config_nested()
  iommu/vt-d: Clear Present bit before tearing down scalable-mode context entry
  iommu/vt-d: Avoid WARNING in sva unbind path
  dt-bindings: arm-smmu: Correct and add constraints for Hawi, Shikra and Kaanapali
  dt-bindings: arm-smmu: Add compatible for Qualcomm Nord SoC
  iommu/amd: Don't split flush for amd_iommu_domain_flush_all()
  iommu/rockchip: disable fetch dte time limit
  iommu/arm-smmu-v3: Allow ATS to be always on
  PCI: Allow ATS to be always on for pre-CXL devices
  PCI: Add pci_ats_required() for CXL.cache capable devices
  iommu/vsi: Use list_for_each_entry()
  ...

3 files changed, 47 insertions, 7 deletions

diff --git a/include/linux/generic_pt/common.h b/include/linux/generic_pt/common.h
index fc5d0b5edadc..07ef1c8341a4 100644
--- a/include/linux/generic_pt/common.h
+++ b/include/linux/generic_pt/common.h
@@ -134,6 +134,11 @@ enum pt_features {
 	 * significant amount of page table.
 	 */
 	PT_FEAT_FLUSH_RANGE_NO_GAPS,
+	/**
+	 * @PT_FEAT_DETAILED_GATHER: Fill in the struct iommu_iotlb_gather pt
+	 * sub structure with information about which levels were changed.
+	 */
+	PT_FEAT_DETAILED_GATHER,
 	/* private: */
 	PT_FEAT_FMT_START,
 };
@@ -188,6 +193,10 @@ enum {
 	 * Support the 64k contiguous page size following the Svnapot extension.
 	 */
 	PT_FEAT_RISCV_SVNAPOT_64K = PT_FEAT_FMT_START,
+	/*
+	 * Support Svpbmt extension: encode page-based memory type (PBMT) in PTEs.
+	 */
+	PT_FEAT_RISCV_SVPBMT,
 
 };
 
diff --git a/include/linux/iommu.h b/include/linux/iommu.h
index e587d4ac4d33..bf8a77a164e4 100644
--- a/include/linux/iommu.h
+++ b/include/linux/iommu.h
@@ -345,12 +345,6 @@ struct iommu_pages_list {
 /**
  * struct iommu_iotlb_gather - Range information for a pending IOTLB flush
  *
- * @start: IOVA representing the start of the range to be flushed
- * @end: IOVA representing the end of the range to be flushed (inclusive)
- * @pgsize: The interval at which to perform the flush
- * @freelist: Removed pages to free after sync
- * @queued: Indicates that the flush will be queued
- *
  * This structure is intended to be updated by multiple calls to the
  * ->unmap() function in struct iommu_ops before eventually being passed
  * into ->iotlb_sync(). Drivers can add pages to @freelist to be freed after
@@ -359,10 +353,44 @@ struct iommu_pages_list {
  * later instead of ->iotlb_sync(), so drivers may optimise accordingly.
  */
 struct iommu_iotlb_gather {
+	/** @start: IOVA representing the start of the range to be flushed */
 	unsigned long		start;
+	/**
+	 * @end: IOVA representing the end of the range to be
+	 *       flushed (inclusive)
+	 */
 	unsigned long		end;
-	size_t			pgsize;
+
+	union {
+		/**
+		 * @pgsize: The interval at which to perform the flush, only
+		 *          used by arm-smmu-v3
+		 */
+		size_t pgsize;
+		struct {
+			/**
+			 * @pt.leaf_levels_bitmap: Bitmap of generic_pt
+			 * levels where leaf entries were unmapped. Bit 0
+			 * means the leaf only level. If 0 no leafs
+			 * were unmapped.
+			 */
+			u8 leaf_levels_bitmap;
+			/**
+			 * @pt.table_levels_bitmap: Bitmap of generic_pt levels
+			 * of table entries that were removed. Bit 0 is never
+			 * set, bit 1 means a table of all leafs was removed.
+			 * When freelist is empty this must be 0.
+			 */
+			u8 table_levels_bitmap;
+		} pt;
+	};
+
+	/**
+	 * @freelist: Removed pages to free after sync, only used by
+	 *            iommupt
+	 */
 	struct iommu_pages_list	freelist;
+	/** @queued: True if the gather will be completed with a flush all */
 	bool			queued;
 };
 
diff --git a/include/linux/pci-ats.h b/include/linux/pci-ats.h
index 75c6c86cf09d..f3723b686129 100644
--- a/include/linux/pci-ats.h
+++ b/include/linux/pci-ats.h
@@ -12,6 +12,7 @@ int pci_prepare_ats(struct pci_dev *dev, int ps);
 void pci_disable_ats(struct pci_dev *dev);
 int pci_ats_queue_depth(struct pci_dev *dev);
 int pci_ats_page_aligned(struct pci_dev *dev);
+bool pci_ats_required(struct pci_dev *dev);
 #else /* CONFIG_PCI_ATS */
 static inline bool pci_ats_supported(struct pci_dev *d)
 { return false; }
@@ -24,6 +25,8 @@ static inline int pci_ats_queue_depth(struct pci_dev *d)
 { return -ENODEV; }
 static inline int pci_ats_page_aligned(struct pci_dev *dev)
 { return 0; }
+static inline bool pci_ats_required(struct pci_dev *dev)
+{ return false; }
 #endif /* CONFIG_PCI_ATS */
 
 #ifdef CONFIG_PCI_PRI