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| author | Jakub Kicinski <kuba@kernel.org> | 2020-11-20 22:01:56 +0300 |
|---|---|---|
| committer | Jakub Kicinski <kuba@kernel.org> | 2020-11-20 22:01:56 +0300 |
| commit | b5fb0b1bbb5021339cfe9e9fe8177a50047545f1 (patch) | |
| tree | 52364630cb8d36c8497b642b02a8540febac8b54 /include/linux | |
| parent | 1a0058cf0c8f5f7ecb2ef2bfe6cfc004d6598769 (diff) | |
| parent | 76638a2e585097c92a77138a354bf03b2af6c851 (diff) | |
| download | linux-b5fb0b1bbb5021339cfe9e9fe8177a50047545f1.tar.xz | |
Merge branch 'add-support-for-marvell-octeontx2-cryptographic'
Srujana Challa says:
====================
Add Support for Marvell OcteonTX2 Cryptographic
This patchset adds support for CPT in OcteonTX2 admin function(AF).
CPT is a cryptographic accelerator unit and it includes microcoded
Giga Cipher engines.
OcteonTX2 SOC's resource virtualization unit (RVU) supports multiple
physical and virtual functions. Each of the PF/VF's functionality is
determined by what kind of resources are attached to it. When the CPT
block is attached to a VF, it can function as a security device.
The following document provides an overview of the hardware and
different drivers for the OcteonTX2 SOC:
https://www.kernel.org/doc/Documentation/networking/device_drivers/marvell/octeontx2.rst
This patch series includes:
- Patch to update existing Marvell sources to support CPT.
- Patch that adds mailbox messages to the admin function (AF) driver,
to configure CPT HW registers.
- Patch to provide debug information about CPT.
====================
Link: https://lore.kernel.org/r/20201118114416.28307-1-schalla@marvell.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
Diffstat (limited to 'include/linux')
| -rw-r--r-- | include/linux/soc/marvell/octeontx2/asm.h | 29 |
1 files changed, 29 insertions, 0 deletions
diff --git a/include/linux/soc/marvell/octeontx2/asm.h b/include/linux/soc/marvell/octeontx2/asm.h new file mode 100644 index 000000000000..ae2279fe830a --- /dev/null +++ b/include/linux/soc/marvell/octeontx2/asm.h @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0-only + * Copyright (C) 2020 Marvell. + */ + +#ifndef __SOC_OTX2_ASM_H +#define __SOC_OTX2_ASM_H + +#if defined(CONFIG_ARM64) +/* + * otx2_lmt_flush is used for LMT store operation. + * On octeontx2 platform CPT instruction enqueue and + * NIX packet send are only possible via LMTST + * operations and it uses LDEOR instruction targeting + * the coprocessor address. + */ +#define otx2_lmt_flush(ioaddr) \ +({ \ + u64 result = 0; \ + __asm__ volatile(".cpu generic+lse\n" \ + "ldeor xzr, %x[rf], [%[rs]]" \ + : [rf]"=r" (result) \ + : [rs]"r" (ioaddr)); \ + (result); \ +}) +#else +#define otx2_lmt_flush(ioaddr) ({ 0; }) +#endif + +#endif /* __SOC_OTX2_ASM_H */ |