diff options
| author | Miquel Raynal <miquel.raynal@bootlin.com> | 2025-04-03 12:19:11 +0300 |
|---|---|---|
| committer | Miquel Raynal <miquel.raynal@bootlin.com> | 2025-04-28 11:24:39 +0300 |
| commit | b15d97139ff14beb7c300f261e11d22d5a996941 (patch) | |
| tree | 28a1b5418b214e3dc8fb489b37ccee655c5be4ac /include/linux | |
| parent | d2d10ede04b1671dc4762479a2d06f183aaafbba (diff) | |
| download | linux-b15d97139ff14beb7c300f261e11d22d5a996941.tar.xz | |
mtd: spinand: Use more specific naming for the reset op
SPI operations have been initially described through macros implicitly
implying the use of a single SPI SDR bus. Macros for supporting dual and
quad I/O transfers have been added on top, generally inspired by vendor
vendor naming, followed by DTR operations. Soon we might see octal
and even octal DTR operations as well (including the opcode byte).
Let's clarify what the macro really means by describing the expected bus
topology in the reset macro name.
Reviewed-by: Tudor Ambarus <tudor.ambarus@linaro.org>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Diffstat (limited to 'include/linux')
| -rw-r--r-- | include/linux/mtd/spinand.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/include/linux/mtd/spinand.h b/include/linux/mtd/spinand.h index 311f145eb4e8..d1b9b630bd83 100644 --- a/include/linux/mtd/spinand.h +++ b/include/linux/mtd/spinand.h @@ -20,7 +20,7 @@ * Standard SPI NAND flash operations */ -#define SPINAND_RESET_OP \ +#define SPINAND_RESET_1S_0_0_OP \ SPI_MEM_OP(SPI_MEM_OP_CMD(0xff, 1), \ SPI_MEM_OP_NO_ADDR, \ SPI_MEM_OP_NO_DUMMY, \ |