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| author | Will Deacon <will@kernel.org> | 2020-12-08 17:45:10 +0300 |
|---|---|---|
| committer | Will Deacon <will@kernel.org> | 2020-12-08 17:45:10 +0300 |
| commit | 75c75adce44f59e6878117d47ad63682c5e5ff87 (patch) | |
| tree | eb3f4081952bb897af432e9f7444789f18f8d630 /include/linux | |
| parent | f8394f232b1eab649ce2df5c5f15b0e528c92091 (diff) | |
| parent | 7f575a6087f47cf2a320d32a102be6276e9fd5bc (diff) | |
| download | linux-75c75adce44f59e6878117d47ad63682c5e5ff87.tar.xz | |
Merge branch 'for-next/iommu/arm-smmu' into for-next/iommu/core
Arm SMMU updates for 5.11, including support for the SMMU integrated
into the Adreno GPU as well as workarounds for the broken firmware
implementation in the DB845c SoC from Qualcomm.
* for-next/iommu/arm-smmu:
iommu: arm-smmu-impl: Add a space before open parenthesis
iommu: arm-smmu-impl: Use table to list QCOM implementations
iommu/arm-smmu: Move non-strict mode to use io_pgtable_domain_attr
iommu/arm-smmu: Add support for pagetable config domain attribute
iommu/io-pgtable-arm: Add support to use system cache
iommu/io-pgtable: Add a domain attribute for pagetable configuration
dt-bindings: arm-smmu: Add compatible string for Adreno GPU SMMU
iommu/arm-smmu: Add a way for implementations to influence SCTLR
iommu/arm-smmu-qcom: Add implementation for the adreno GPU SMMU
iommu/arm-smmu-v3: Assign boolean values to a bool variable
iommu/arm-smmu: Use new devm_krealloc()
iommu/arm-smmu-qcom: Implement S2CR quirk
iommu/arm-smmu-qcom: Read back stream mappings
iommu/arm-smmu: Allow implementation specific write_s2cr
Diffstat (limited to 'include/linux')
| -rw-r--r-- | include/linux/io-pgtable.h | 8 | ||||
| -rw-r--r-- | include/linux/iommu.h | 1 |
2 files changed, 9 insertions, 0 deletions
diff --git a/include/linux/io-pgtable.h b/include/linux/io-pgtable.h index 4cde111e425b..fb4d5a763e0c 100644 --- a/include/linux/io-pgtable.h +++ b/include/linux/io-pgtable.h @@ -86,6 +86,9 @@ struct io_pgtable_cfg { * * IO_PGTABLE_QUIRK_ARM_TTBR1: (ARM LPAE format) Configure the table * for use in the upper half of a split address space. + * + * IO_PGTABLE_QUIRK_ARM_OUTER_WBWA: Override the outer-cacheability + * attributes set in the TCR for a non-coherent page-table walker. */ #define IO_PGTABLE_QUIRK_ARM_NS BIT(0) #define IO_PGTABLE_QUIRK_NO_PERMS BIT(1) @@ -93,6 +96,7 @@ struct io_pgtable_cfg { #define IO_PGTABLE_QUIRK_ARM_MTK_EXT BIT(3) #define IO_PGTABLE_QUIRK_NON_STRICT BIT(4) #define IO_PGTABLE_QUIRK_ARM_TTBR1 BIT(5) + #define IO_PGTABLE_QUIRK_ARM_OUTER_WBWA BIT(6) unsigned long quirks; unsigned long pgsize_bitmap; unsigned int ias; @@ -208,6 +212,10 @@ struct io_pgtable { #define io_pgtable_ops_to_pgtable(x) container_of((x), struct io_pgtable, ops) +struct io_pgtable_domain_attr { + unsigned long quirks; +}; + static inline void io_pgtable_tlb_flush_all(struct io_pgtable *iop) { iop->cfg.tlb->tlb_flush_all(iop->cookie); diff --git a/include/linux/iommu.h b/include/linux/iommu.h index b95a6f8db6ff..ffaa389ea128 100644 --- a/include/linux/iommu.h +++ b/include/linux/iommu.h @@ -118,6 +118,7 @@ enum iommu_attr { DOMAIN_ATTR_FSL_PAMUV1, DOMAIN_ATTR_NESTING, /* two stages of translation */ DOMAIN_ATTR_DMA_USE_FLUSH_QUEUE, + DOMAIN_ATTR_IO_PGTABLE_CFG, DOMAIN_ATTR_MAX, }; |