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authorPierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>2024-10-03 10:06:50 +0300
committerVinod Koul <vkoul@kernel.org>2024-10-03 10:58:51 +0300
commit71b405b184449fffcb76ea0814104b71dfdb2aee (patch)
tree825e0667702ae4ed30c760c61f25fbabbd18c86a /include/linux
parent543bd28a3bfeff31f748ba83348b63313dd37ff9 (diff)
downloadlinux-71b405b184449fffcb76ea0814104b71dfdb2aee.tar.xz
soundwire: mipi-disco: add support for DP0/DPn 'lane-list' property
The SoundWire specification did not clearly require that ports could use all Lanes. Some SoundWire/SDCA peripheral adopters added restrictions on which lanes can be used by what port, and the DisCo for SoundWire 2.1 specification added a 'lane-list' property to model this hardware limitation. When not specified, the ports can use all Lanes. Otherwise, the 'lane-list' indicates which Lanes can be used, sorted by order of preference (most-preferred-first). This patch only reads the properties, the use of this property will come at a later time with multi-lane support. Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com> Signed-off-by: Bard Liao <yung-chuan.liao@linux.intel.com> Link: https://lore.kernel.org/r/20241003070650.62787-15-yung-chuan.liao@linux.intel.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
Diffstat (limited to 'include/linux')
-rw-r--r--include/linux/soundwire/sdw.h8
1 files changed, 8 insertions, 0 deletions
diff --git a/include/linux/soundwire/sdw.h b/include/linux/soundwire/sdw.h
index 952514f044f0..73f655334fe9 100644
--- a/include/linux/soundwire/sdw.h
+++ b/include/linux/soundwire/sdw.h
@@ -238,6 +238,8 @@ enum sdw_clk_stop_mode {
* @simple_ch_prep_sm: If channel prepare sequence is required
* @imp_def_interrupts: If set, each bit corresponds to support for
* implementation-defined interrupts
+ * @num_lanes: array size of @lane_list
+ * @lane_list: indicates which Lanes can be used by DP0
*
* The wordlengths are specified by Spec as max, min AND number of
* discrete values, implementation can define based on the wordlengths they
@@ -252,6 +254,8 @@ struct sdw_dp0_prop {
bool BRA_flow_controlled;
bool simple_ch_prep_sm;
bool imp_def_interrupts;
+ int num_lanes;
+ u32 *lane_list;
};
/**
@@ -275,6 +279,8 @@ struct sdw_dp0_prop {
* @num_ch_combinations: Number of channel combinations supported
* @channels: Discrete channels supported
* @ch_combinations: Channel combinations supported
+ * @lane_list: indicates which Lanes can be used by DPn
+ * @num_lanes: array size of @lane_list
* @modes: SDW mode supported
* @max_async_buffer: Number of samples that this port can buffer in
* asynchronous modes
@@ -300,6 +306,8 @@ struct sdw_dpn_prop {
u32 num_ch_combinations;
u32 *channels;
u32 *ch_combinations;
+ u32 *lane_list;
+ int num_lanes;
u32 modes;
u32 max_async_buffer;
u32 port_encoding;