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| author | Albert Yang <yangzh0906@thundersoft.com> | 2026-06-12 03:40:23 +0300 |
|---|---|---|
| committer | Gordon Ge <gordon.ge@bst.ai> | 2026-06-12 09:17:45 +0300 |
| commit | 6191a61ec9d9d8f1d1d1d6bfcb6d303be76c2804 (patch) | |
| tree | 84f1729b74a4f922724c1eb17ef64f1016d629ec /include/linux | |
| parent | 254f49634ee16a731174d2ae34bc50bd5f45e731 (diff) | |
| download | linux-6191a61ec9d9d8f1d1d1d6bfcb6d303be76c2804.tar.xz | |
arm64: dts: bst: enable eMMC controller in C1200
Add mmc0 node for the DWCMSHC SDHCI controller with basic configuration
(disabled by default) and fixed clock definition in bstc1200.dtsi.
Enable mmc0 with board-specific configuration including 8-bit bus
width and reserved SRAM bounce buffer on the CDCU1.0 ADAS 4C2G board.
The bounce buffer in reserved SRAM addresses hardware constraints
where the eMMC controller cannot access main system memory through
SMMU due to a hardware bug, and all DRAM is located outside the
4GB boundary.
Signed-off-by: Albert Yang <yangzh0906@thundersoft.com>
Acked-by: Gordon Ge <gordon.ge@bst.ai>
Signed-off-by: Gordon Ge <gordon.ge@bst.ai>
Diffstat (limited to 'include/linux')
0 files changed, 0 insertions, 0 deletions