Merge tag 'pinctrl-v6.15-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

Pull pin control updates from Linus Walleij:
 "Core changes:

   - None really.

  New drivers:

   - AMD ISP411 "AMD ISP" driver

   - Exynos 2200 and 7870 SoC subdrivers

   - Sophgo RISC-V SG2042 and SG2044 subdrivers

   - Amlogic A4 subdriver

   - Rockchip RK3528 subdriver

   - Broadcom BCM21664 subdriver

   - Allwinner A523/T527 subdriver

   - Ingenic X1600 subdriver

   - Microchip SAMA7D65 subdriver, essentially a re-branded Atmel AT91
     PIO4 driver, but nowadays a Microschip SoC line

  Improvements:

   - Bring in the devm_kmemdup_array() helper and use it throughout,
     also bring in changes to other subsystems for this to establish
     this helper

   - Support EGPIO on the Qualcomm SA8775P SoC

   - Extend EINT support in the Mediatek driver"

* tag 'pinctrl-v6.15-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (101 commits)
  pinctrl: mediatek: Add EINT support for multiple addresses
  pinctrl: amlogic-a4: Drop surplus semicolon
  pinctrl: nuvoton: Reduce use of OF-specific APIs
  pinctrl: nuvoton: Convert to use struct group_desc
  pinctrl: nuvoton: Make use of struct pinfunction and PINCTRL_PINFUNCTION()
  pinctrl: nuvoton: Convert to use struct pingroup and PINCTRL_PINGROUP()
  pinctrl: npcm8xx: Fix incorrect struct npcm8xx_pincfg assignment
  pinctrl: tegra: Fix off by one in tegra_pinctrl_get_group()
  pinctrl: PINCTRL_AMDISP should depend on DRM_AMD_ISP
  pinctrl: qcom: sa8775p: Enable egpio function
  dt-bindings: pinctrl: qcom: Add egpio function for sa8775p
  pinctrl: qcom: tlmm-test: Validate irq_enable delivers edge irqs
  pinctrl: qcom: Clear latched interrupt status when changing IRQ type
  dt-bindings: pinctrl: airoha: Add missing gpio-ranges property
  pinctrl: bcm281xx: Add missing assignment in bcm21664_pinctrl_lock_all()
  pinctrl: amd: isp411: Fix IS_ERR() vs NULL check in probe()
  dt-bindings: pinctrl: at91-pio4: add microchip,sama7d65-pinctrl
  pinctrl: tegra: Set SFIO mode to Mux Register
  pinctrl-tegra: Restore SFSEL bit when freeing pins
  pinctrl: tegra: Add descriptions for SoC data fields
  ...

2 files changed, 34 insertions, 3 deletions

diff --git a/include/linux/pinctrl/pinconf-generic.h b/include/linux/pinctrl/pinconf-generic.h
index 53cfde98433d..1bcf071b860e 100644
--- a/include/linux/pinctrl/pinconf-generic.h
+++ b/include/linux/pinctrl/pinconf-generic.h
@@ -232,4 +232,8 @@ static inline int pinconf_generic_dt_node_to_map_all(struct pinctrl_dev *pctldev
 			PIN_MAP_TYPE_INVALID);
 }
 
+int pinconf_generic_dt_node_to_map_pinmux(struct pinctrl_dev *pctldev,
+					  struct device_node *np,
+					  struct pinctrl_map **map,
+					  unsigned int *num_maps);
 #endif /* __LINUX_PINCTRL_PINCONF_GENERIC_H */
diff --git a/include/linux/platform_data/x86/pwm-lpss.h b/include/linux/platform_data/x86/pwm-lpss.h
index 752c06b47cc8..f0349edb47f4 100644
--- a/include/linux/platform_data/x86/pwm-lpss.h
+++ b/include/linux/platform_data/x86/pwm-lpss.h
@@ -15,9 +15,36 @@ struct pwm_lpss_boardinfo {
 	unsigned int npwm;
 	unsigned long base_unit_bits;
 	/*
-	 * Some versions of the IP may stuck in the state machine if enable
-	 * bit is not set, and hence update bit will show busy status till
-	 * the reset. For the rest it may be otherwise.
+	 * NOTE:
+	 * Intel Broxton, Apollo Lake, and Gemini Lake have different programming flow.
+	 *
+	 * Initial Enable or First Activation
+	 * 1. Program the base unit and on time divisor values.
+	 * 2. Set the software update bit.
+	 * 3. Poll in a loop on the PWMCTRL bit until software update bit is cleared.+
+	 * 4. Enable the PWM output by setting PWM Enable.
+	 * 5. Repeat the above steps for the next PWM Module.
+	 *
+	 * Dynamic update while PWM is Enabled
+	 * 1. Program the base unit and on-time divisor values.
+	 * 2. Set the software update bit.
+	 * 3. Repeat the above steps for the next PWM module.
+	 *
+	 * + After setting PWMCTRL register's SW update bit, hardware automatically
+	 * deasserts the SW update bit after a brief delay. It was observed that
+	 * setting of PWM enable is typically done via read-modify-write of the PWMCTRL
+	 * register. If there is no/little delay between setting software update bit
+	 * and setting enable bit via read-modify-write, it is possible that the read
+	 * could return with software enable as 1. In that case, the last write to set
+	 * enable to 1 could also set sw_update to 1. If this happens, sw_update gets
+	 * stuck and the driver code can hang as it explicitly waits for sw_update bit
+	 * to be 0 after setting the enable bit to 1. To avoid this race condition,
+	 * SW should poll on the software update bit to make sure that it is 0 before
+	 * doing the read-modify-write to set the enable bit to 1.
+	 *
+	 * Also, we noted that if sw_update bit was set in step #1 above then when it
+	 * is set again in step #2, sw_update bit never gets cleared and the flow hangs.
+	 * As such, we need to make sure that sw_update bit is 0 when doing step #1.
 	 */
 	bool bypass;
 	/*