Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

Pull clk updates from Stephen Boyd:
 "Not much changed in the clk framework this time except the clk.h
  consumer API moved the context saving APIs around to fix a build error
  in certain configurations.

  There was a change to the core framework for CLK_OPS_PARENT_ENABLE
  behavior during registration, but it wrecked existing drivers that
  didn't expect things to be turned off during clk registration so it
  got reverted.

  This cycle is really a large collection of new clk drivers, primarily
  for Qualcomm SoCs but also for Amlogic, SpacemiT, Google, and Aspeed.
  Another big change in here is support for automatic hardware clock
  gating on Samsung SoCs where the clks turn on and off when needed.
  Ideally more vendors move to this method for better power savings. The
  highlights are in the updates section below.

  Beyond all the new drivers we have a bunch of cleanups like converting
  drivers from divider_round_rate() to divider_determine_rate() and
  using scoped for each OF child loops. Otherwise it's the usual data
  fixes and plugging reference leaks, etc. that's all pretty ordinary
  but not critical enough to fix until the next release.

  New Drivers:
   - Qualcomm Kaanapali global, tcsr, rpmh, display, gpu, camera, and
     video clk controllers
   - Qualcomm SM8750 camera clk controllers
   - Qualcomm MSM8940 and SDM439 global clk controllers
   - Google GS101 Display Process Unit (DPU) clk controllers
   - SpacemiT K3 clk controllers
   - Amlogic t7 clk controllers
   - Aspeed AST2700 clk controllers

  Updates:
   - Convert clock dividers from round_rate() to determine_rate()
   - Fix sparse warnings, kernel-doc warnings, and plug leaked OF refs
   - Automatic hardware clk gating on Google GS101 SoCs
   - Amlogic s4 video clks
   - CAN-FD clks and resets on Renesas RZ/T2H, RZ/N2H, RZ/V2H, and
     RZ/V2N
   - Expanded Serial Peripheral Interface (xSPI) clocks and resets on
     Renesas RZ/T21H and RZ/N2H
   - DMAC, interrupt controller (ICU), SPI, and thermal (TSU) clocks and
     resets on Renesas RZ/V2N
   - More serial (RSCI) clocks and resets on Renesas RZ/V2H and RZ/V2N
   - CPU frequency scaling on T-HEAD TH1520"

* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (165 commits)
  clk: aspeed: Add reset for HACE/VIDEO
  dt-bindings: clock: aspeed: Add VIDEO reset definition
  clk: aspeed: add AST2700 clock driver
  MAINTAINERS: Add entry for ASPEED clock drivers.
  clk: aspeed: Move the existing ASPEED clk drivers into aspeed subdirectory.
  Revert "clk: Respect CLK_OPS_PARENT_ENABLE during recalc"
  clk: Disable KUNIT_UML_PCI
  dt-bindings: clk: rs9: Fix DIF pattern match
  clk: rs9: Convert to DEFINE_SIMPLE_DEV_PM_OPS()
  clk: rs9: Reserve 8 struct clk_hw slots for for 9FGV0841
  clk: qcom: sm8750: Constify 'qcom_cc_desc' in SM8750 camcc
  clk: zynqmp: pll: Fix zynqmp_clk_divider_determine_rate kerneldoc
  clk: zynqmp: divider: Fix zynqmp_clk_divider_determine_rate kerneldoc
  clk: mediatek: Fix error handling in runtime PM setup
  clk: mediatek: don't select clk-mt8192 for all ARM64 builds
  clk: mediatek: Add mfg_eb as parent to mt8196 mfgpll clocks
  clk: mediatek: Refactor pllfh registration to pass device
  clk: mediatek: Pass device to clk_hw_register for PLLs
  clk: mediatek: Refactor pll registration to pass device
  clk: Respect CLK_OPS_PARENT_ENABLE during recalc
  ...

2 files changed, 63 insertions, 52 deletions

diff --git a/include/linux/clk.h b/include/linux/clk.h
index c571e294f0ef..998ba3f261da 100644
--- a/include/linux/clk.h
+++ b/include/linux/clk.h
@@ -228,7 +228,24 @@ int devm_clk_rate_exclusive_get(struct device *dev, struct clk *clk);
  */
 void clk_rate_exclusive_put(struct clk *clk);
 
-#else
+/**
+ * clk_save_context - save clock context for poweroff
+ *
+ * Saves the context of the clock register for powerstates in which the
+ * contents of the registers will be lost. Occurs deep within the suspend
+ * code so locking is not necessary.
+ */
+int clk_save_context(void);
+
+/**
+ * clk_restore_context - restore clock context after poweroff
+ *
+ * This occurs with all clocks enabled. Occurs deep within the resume code
+ * so locking is not necessary.
+ */
+void clk_restore_context(void);
+
+#else /* !CONFIG_COMMON_CLK */
 
 static inline int clk_notifier_register(struct clk *clk,
 					struct notifier_block *nb)
@@ -293,7 +310,14 @@ static inline int devm_clk_rate_exclusive_get(struct device *dev, struct clk *cl
 
 static inline void clk_rate_exclusive_put(struct clk *clk) {}
 
-#endif
+static inline int clk_save_context(void)
+{
+	return 0;
+}
+
+static inline void clk_restore_context(void) {}
+
+#endif /* !CONFIG_COMMON_CLK */
 
 #ifdef CONFIG_HAVE_CLK_PREPARE
 /**
@@ -305,8 +329,21 @@ static inline void clk_rate_exclusive_put(struct clk *clk) {}
  * Must not be called from within atomic context.
  */
 int clk_prepare(struct clk *clk);
+
+/**
+ * clk_unprepare - undo preparation of a clock source
+ * @clk: clock source
+ *
+ * This undoes a previously prepared clock.  The caller must balance
+ * the number of prepare and unprepare calls.
+ *
+ * Must not be called from within atomic context.
+ */
+void clk_unprepare(struct clk *clk);
+
 int __must_check clk_bulk_prepare(int num_clks,
 				  const struct clk_bulk_data *clks);
+void clk_bulk_unprepare(int num_clks, const struct clk_bulk_data *clks);
 
 /**
  * clk_is_enabled_when_prepared - indicate if preparing a clock also enables it.
@@ -324,49 +361,36 @@ int __must_check clk_bulk_prepare(int num_clks,
  * to be right.
  */
 bool clk_is_enabled_when_prepared(struct clk *clk);
-#else
+#else /* !CONFIG_HAVE_CLK_PREPARE */
 static inline int clk_prepare(struct clk *clk)
 {
 	might_sleep();
 	return 0;
 }
 
-static inline int __must_check
-clk_bulk_prepare(int num_clks, const struct clk_bulk_data *clks)
+static inline void clk_unprepare(struct clk *clk)
 {
 	might_sleep();
-	return 0;
 }
 
-static inline bool clk_is_enabled_when_prepared(struct clk *clk)
-{
-	return false;
-}
-#endif
-
-/**
- * clk_unprepare - undo preparation of a clock source
- * @clk: clock source
- *
- * This undoes a previously prepared clock.  The caller must balance
- * the number of prepare and unprepare calls.
- *
- * Must not be called from within atomic context.
- */
-#ifdef CONFIG_HAVE_CLK_PREPARE
-void clk_unprepare(struct clk *clk);
-void clk_bulk_unprepare(int num_clks, const struct clk_bulk_data *clks);
-#else
-static inline void clk_unprepare(struct clk *clk)
+static inline int __must_check
+clk_bulk_prepare(int num_clks, const struct clk_bulk_data *clks)
 {
 	might_sleep();
+	return 0;
 }
+
 static inline void clk_bulk_unprepare(int num_clks,
 				      const struct clk_bulk_data *clks)
 {
 	might_sleep();
 }
-#endif
+
+static inline bool clk_is_enabled_when_prepared(struct clk *clk)
+{
+	return false;
+}
+#endif /* !CONFIG_HAVE_CLK_PREPARE */
 
 #ifdef CONFIG_HAVE_CLK
 /**
@@ -949,23 +973,6 @@ struct clk *clk_get_parent(struct clk *clk);
  */
 struct clk *clk_get_sys(const char *dev_id, const char *con_id);
 
-/**
- * clk_save_context - save clock context for poweroff
- *
- * Saves the context of the clock register for powerstates in which the
- * contents of the registers will be lost. Occurs deep within the suspend
- * code so locking is not necessary.
- */
-int clk_save_context(void);
-
-/**
- * clk_restore_context - restore clock context after poweroff
- *
- * This occurs with all clocks enabled. Occurs deep within the resume code
- * so locking is not necessary.
- */
-void clk_restore_context(void);
-
 #else /* !CONFIG_HAVE_CLK */
 
 static inline struct clk *clk_get(struct device *dev, const char *id)
@@ -1152,14 +1159,7 @@ static inline struct clk *clk_get_sys(const char *dev_id, const char *con_id)
 	return NULL;
 }
 
-static inline int clk_save_context(void)
-{
-	return 0;
-}
-
-static inline void clk_restore_context(void) {}
-
-#endif
+#endif /* !CONFIG_HAVE_CLK */
 
 /* clk_prepare_enable helps cases using clk_enable in non-atomic context. */
 static inline int clk_prepare_enable(struct clk *clk)
diff --git a/include/linux/clk/renesas.h b/include/linux/clk/renesas.h
index 69d8159deee3..c360df9fa735 100644
--- a/include/linux/clk/renesas.h
+++ b/include/linux/clk/renesas.h
@@ -35,6 +35,17 @@ void cpg_mssr_detach_dev(struct generic_pm_domain *unused, struct device *dev);
 #define cpg_mssr_detach_dev	NULL
 #endif
 
+enum {
+	PLL5_TARGET_DPI,
+	PLL5_TARGET_DSI
+};
+
+#ifdef CONFIG_CLK_RZG2L
+void rzg2l_cpg_dsi_div_set_divider(u8 divider, int target);
+#else
+static inline void rzg2l_cpg_dsi_div_set_divider(u8 divider, int target) { }
+#endif
+
 /**
  * struct rzv2h_pll_limits - PLL parameter constraints
  *