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| author | Palmer Dabbelt <palmer@rivosinc.com> | 2024-02-15 19:04:23 +0300 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@rivosinc.com> | 2024-02-15 19:04:23 +0300 |
| commit | 0420af54c2c2b7b3abbd986a41aded7cab0137ef (patch) | |
| tree | 955c76570472c23549e14c043535b8faca14b74e /include/linux | |
| parent | cb4ede926134a65bc3bf90ed58dace8451d7e759 (diff) | |
| parent | cd9b29014dc69609489261efe351d0c7709ae8bf (diff) | |
| download | linux-0420af54c2c2b7b3abbd986a41aded7cab0137ef.tar.xz | |
Merge patch series "membarrier: riscv: Core serializing command"
RISC-V was lacking a membarrier implementation for the store/fetch
ordering, which is a bit tricky because of the deferred icache flushing
we use in RISC-V.
* b4-shazam-merge:
membarrier: riscv: Provide core serializing command
locking: Introduce prepare_sync_core_cmd()
membarrier: Create Documentation/scheduler/membarrier.rst
membarrier: riscv: Add full memory barrier in switch_mm()
Link: https://lore.kernel.org/r/20240131144936.29190-1-parri.andrea@gmail.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Diffstat (limited to 'include/linux')
| -rw-r--r-- | include/linux/sync_core.h | 16 |
1 files changed, 15 insertions, 1 deletions
diff --git a/include/linux/sync_core.h b/include/linux/sync_core.h index 013da4b8b327..67bb9794b875 100644 --- a/include/linux/sync_core.h +++ b/include/linux/sync_core.h @@ -17,5 +17,19 @@ static inline void sync_core_before_usermode(void) } #endif -#endif /* _LINUX_SYNC_CORE_H */ +#ifdef CONFIG_ARCH_HAS_PREPARE_SYNC_CORE_CMD +#include <asm/sync_core.h> +#else +/* + * This is a dummy prepare_sync_core_cmd() implementation that can be used on + * all architectures which provide unconditional core serializing instructions + * in switch_mm(). + * If your architecture doesn't provide such core serializing instructions in + * switch_mm(), you may need to write your own functions. + */ +static inline void prepare_sync_core_cmd(struct mm_struct *mm) +{ +} +#endif +#endif /* _LINUX_SYNC_CORE_H */ |