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| author | Fabrizio Castro <fabrizio.castro.jz@renesas.com> | 2026-05-15 00:02:17 +0300 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2026-05-31 11:49:18 +0300 |
| commit | a6c4c7114b5b4ffe3685fe26002eccd40eb11f3c (patch) | |
| tree | 019fd6590ac67dece234d3bb72693f47ac2c42ae /include/linux/timerqueue.h | |
| parent | 54613573ff1495b928e2841b257c081a58566901 (diff) | |
| download | linux-a6c4c7114b5b4ffe3685fe26002eccd40eb11f3c.tar.xz | |
arm64: dts: renesas: rzt2h-n2h-evk: Configure eMMC/SDHI pins
The HW user manual for the Renesas RZ/T2H and the RZ/N2H states that for
SDR104, SDR50, and HS200 to work properly the eMMC/SDHI interface pins
have to be configured as specified below:
- SDn_CLK pin - drive strength: Ultra High, slew rate: Fast,
- Other SDn_* pins: drive strength: High, slew rate: Fast,
Schmitt trigger: disabled (not applicable to SDn_RST pins).
HS DDR and DDR50 are currently not supported, and for every other bus
mode the eMMC/SDHI interface pins should be configured as specified
below:
- SDn_CLK pin - drive strength: High, slew rate: Fast,
- Other SDn_* pins: drive strength: Middle, slew rate: Fast,
Schmitt trigger: disabled (not applicable to SDn_RST pins).
Adjust the pin definitions accordingly.
Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://patch.msgid.link/20260514210220.7616-1-fabrizio.castro.jz@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'include/linux/timerqueue.h')
0 files changed, 0 insertions, 0 deletions