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| author | Dominique Belhachemi <domibel@debian.org> | 2026-04-30 06:52:59 +0300 |
|---|---|---|
| committer | Conor Dooley <conor.dooley@microchip.com> | 2026-05-21 13:12:00 +0300 |
| commit | 8e2501e1494c8d27f62eb8d36bba5af465f48962 (patch) | |
| tree | 1703cc2fb42cf79603b38df0895b32db8a953e26 /include/linux/timerqueue.h | |
| parent | 254f49634ee16a731174d2ae34bc50bd5f45e731 (diff) | |
| download | linux-8e2501e1494c8d27f62eb8d36bba5af465f48962.tar.xz | |
cache: sifive_ccache: Add StarFive JH7110 SoC support
This cache controller is also used on the StarFive JH7110 SoC. It does
not have the data-uncorrectable ECC quirk that JH7100 has, so only
QUIRK_NONSTANDARD_CACHE_OPS is set.
Signed-off-by: Dominique Belhachemi <domibel@debian.org>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Diffstat (limited to 'include/linux/timerqueue.h')
0 files changed, 0 insertions, 0 deletions