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| author | John Madieu <john.madieu.xa@bp.renesas.com> | 2026-05-25 14:02:22 +0300 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2026-06-01 17:30:20 +0300 |
| commit | 80f43c5217715641a3147eb223677e3c1600e65b (patch) | |
| tree | cf93e6cc43f348b1e1b275569ddb790540074275 /include/linux/timerqueue.h | |
| parent | b4ef837a28a100dfafff05463e11ff00d52fb411 (diff) | |
| download | linux-80f43c5217715641a3147eb223677e3c1600e65b.tar.xz | |
ASoC: rsnd: ssiu: Add RZ/G3E BUSIF support
Add support for the SSIU found on the Renesas RZ/G3E SoC, which
provides a different BUSIF layout compared to earlier generations:
- SSI0-SSI4: 4 BUSIF instances each (BUSIF0-3)
- SSI5-SSI8: 1 BUSIF instance each (BUSIF0 only)
- SSI9: 4 BUSIF instances (BUSIF0-3)
- Total: 28 BUSIFs
The RZ/G3E also has only two pairs of BUSIF error-status registers
instead of four, and the SSI always operates in BUSIF mode: the
SSI_MODE0 BUSIF/PIO select bit is not implemented and must not be written.
While at it, add RSND_SSIU_BUSIF_STATUS_COUNT_2 as a capability flag in
the match data, consumed via struct rsnd_ssiu_ctrl, to parametrise the two
BUSIF error-status loops.
Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
Acked-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Link: https://patch.msgid.link/20260525110230.4014435-11-john.madieu.xa@bp.renesas.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'include/linux/timerqueue.h')
0 files changed, 0 insertions, 0 deletions