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authorAlexei Lazar <alazar@nvidia.com>2025-10-22 15:29:39 +0300
committerJakub Kicinski <kuba@kernel.org>2025-10-23 17:14:32 +0300
commitbb65e0c141f879cdf54db11ae446ee3605fb54d5 (patch)
tree38b22ffb567f15b7be32fa2b531fa945b0f8cbfb /include/linux/mlx5
parentb2284768c6b32aa224ca7d0ef0741beb434f03aa (diff)
downloadlinux-bb65e0c141f879cdf54db11ae446ee3605fb54d5.tar.xz
net/mlx5: Add PPHCR to PCAM supported registers mask
Add the PPHCR bit to the port_access_reg_cap_mask field of PCAM register to indicate that the device supports the PPHCR register and the RS-FEC histogram feature. Signed-off-by: Alexei Lazar <alazar@nvidia.com> Reviewed-by: Yael Chemla <ychemla@nvidia.com> Signed-off-by: Tariq Toukan <tariqt@nvidia.com> Link: https://patch.msgid.link/1761136182-918470-2-git-send-email-tariqt@nvidia.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
Diffstat (limited to 'include/linux/mlx5')
-rw-r--r--include/linux/mlx5/mlx5_ifc.h4
1 files changed, 3 insertions, 1 deletions
diff --git a/include/linux/mlx5/mlx5_ifc.h b/include/linux/mlx5/mlx5_ifc.h
index 07614cd95bed..1b0b36aa2a76 100644
--- a/include/linux/mlx5/mlx5_ifc.h
+++ b/include/linux/mlx5/mlx5_ifc.h
@@ -10833,7 +10833,9 @@ struct mlx5_ifc_pcam_regs_5000_to_507f_bits {
u8 port_access_reg_cap_mask_127_to_96[0x20];
u8 port_access_reg_cap_mask_95_to_64[0x20];
- u8 port_access_reg_cap_mask_63_to_36[0x1c];
+ u8 port_access_reg_cap_mask_63[0x1];
+ u8 pphcr[0x1];
+ u8 port_access_reg_cap_mask_61_to_36[0x1a];
u8 pplm[0x1];
u8 port_access_reg_cap_mask_34_to_32[0x3];