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| author | Marc Zyngier <marc.zyngier@arm.com> | 2015-09-30 13:48:01 +0300 |
|---|---|---|
| committer | Marc Zyngier <marc.zyngier@arm.com> | 2015-10-10 00:16:52 +0300 |
| commit | 7cabd0086acd8f204d9b11a9b0aca90d6a9fcc5b (patch) | |
| tree | 074a43d5bd64bfdb86d9682953b292c625408813 /include/linux/irqchip/arm-gic-v3.h | |
| parent | d271976dbb31c3ac5653745d03d68c4235d34119 (diff) | |
| download | linux-7cabd0086acd8f204d9b11a9b0aca90d6a9fcc5b.tar.xz | |
irqchip/gic-v3: Make gic_enable_sre an inline function
In order for gic_enable_sre to be used by the arm64 core code,
move it to arm-gic-v3.h. As a bonus, we now also check if
system registers have been already enabled, and return early
if they have.
In all cases, the function now returns a boolean indicating if
the enabling has been successful.
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Diffstat (limited to 'include/linux/irqchip/arm-gic-v3.h')
| -rw-r--r-- | include/linux/irqchip/arm-gic-v3.h | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/include/linux/irqchip/arm-gic-v3.h b/include/linux/irqchip/arm-gic-v3.h index c0c8a2ef9d90..9001b0bbe878 100644 --- a/include/linux/irqchip/arm-gic-v3.h +++ b/include/linux/irqchip/arm-gic-v3.h @@ -398,6 +398,22 @@ static inline void gic_write_dir(u64 irq) isb(); } +static inline bool gic_enable_sre(void) +{ + u64 val; + + asm volatile("mrs_s %0, " __stringify(ICC_SRE_EL1) : "=r" (val)); + if (val & ICC_SRE_EL1_SRE) + return true; + + val |= ICC_SRE_EL1_SRE; + asm volatile("msr_s " __stringify(ICC_SRE_EL1) ", %0" : : "r" (val)); + isb(); + asm volatile("mrs_s %0, " __stringify(ICC_SRE_EL1) : "=r" (val)); + + return !!(val & ICC_SRE_EL1_SRE); +} + struct irq_domain; int its_cpu_init(void); int its_init(struct device_node *node, struct rdists *rdists, |