From 7cabd0086acd8f204d9b11a9b0aca90d6a9fcc5b Mon Sep 17 00:00:00 2001 From: Marc Zyngier Date: Wed, 30 Sep 2015 11:48:01 +0100 Subject: irqchip/gic-v3: Make gic_enable_sre an inline function In order for gic_enable_sre to be used by the arm64 core code, move it to arm-gic-v3.h. As a bonus, we now also check if system registers have been already enabled, and return early if they have. In all cases, the function now returns a boolean indicating if the enabling has been successful. Reviewed-by: Catalin Marinas Signed-off-by: Marc Zyngier --- include/linux/irqchip/arm-gic-v3.h | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) (limited to 'include/linux/irqchip/arm-gic-v3.h') diff --git a/include/linux/irqchip/arm-gic-v3.h b/include/linux/irqchip/arm-gic-v3.h index c0c8a2ef9d90..9001b0bbe878 100644 --- a/include/linux/irqchip/arm-gic-v3.h +++ b/include/linux/irqchip/arm-gic-v3.h @@ -398,6 +398,22 @@ static inline void gic_write_dir(u64 irq) isb(); } +static inline bool gic_enable_sre(void) +{ + u64 val; + + asm volatile("mrs_s %0, " __stringify(ICC_SRE_EL1) : "=r" (val)); + if (val & ICC_SRE_EL1_SRE) + return true; + + val |= ICC_SRE_EL1_SRE; + asm volatile("msr_s " __stringify(ICC_SRE_EL1) ", %0" : : "r" (val)); + isb(); + asm volatile("mrs_s %0, " __stringify(ICC_SRE_EL1) : "=r" (val)); + + return !!(val & ICC_SRE_EL1_SRE); +} + struct irq_domain; int its_cpu_init(void); int its_init(struct device_node *node, struct rdists *rdists, -- cgit v1.2.3