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| author | Joonas Lahtinen <joonas.lahtinen@linux.intel.com> | 2022-04-12 11:28:42 +0300 |
|---|---|---|
| committer | Joonas Lahtinen <joonas.lahtinen@linux.intel.com> | 2022-04-12 11:28:42 +0300 |
| commit | c16c8bfa09d5f318c1bd65698d058d3739970c24 (patch) | |
| tree | a3ac5a1cad695c93d698cfff0b7629fd1a2ff79c /include/linux/cacheflush.h | |
| parent | 8e7e5c077cd57ee9a36d58c65f07257dc49a88d5 (diff) | |
| parent | b85ffe47c4ec172214a38b7e7087c60582c488f0 (diff) | |
| download | linux-c16c8bfa09d5f318c1bd65698d058d3739970c24.tar.xz | |
Merge drm/drm-next into drm-intel-gt-next
Pull in TTM changes needed for DG2 CCS enabling from Ram.
Signed-off-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Diffstat (limited to 'include/linux/cacheflush.h')
| -rw-r--r-- | include/linux/cacheflush.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/include/linux/cacheflush.h b/include/linux/cacheflush.h index fef8b607f97e..a6189d21f2ba 100644 --- a/include/linux/cacheflush.h +++ b/include/linux/cacheflush.h @@ -4,6 +4,8 @@ #include <asm/cacheflush.h> +struct folio; + #if ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE #ifndef ARCH_IMPLEMENTS_FLUSH_DCACHE_FOLIO void flush_dcache_folio(struct folio *folio); |