diff options
| author | Stephen Boyd <sboyd@codeaurora.org> | 2014-07-16 01:52:22 +0400 |
|---|---|---|
| committer | Stephen Boyd <sboyd@codeaurora.org> | 2014-07-16 03:39:03 +0400 |
| commit | e216ce60a9e05ab399d098f05cd86fd95c9da8d5 (patch) | |
| tree | e4011df8185206e60764bb528e3be601c15a5668 /include/dt-bindings | |
| parent | d8c25d3a1a1d61cf433654f3632a03ddaee4f781 (diff) | |
| download | linux-e216ce60a9e05ab399d098f05cd86fd95c9da8d5.tar.xz | |
clk: qcom: Add support for APQ8064 multimedia clocks
The APQ8064 multimedia clock controller is fairly similar to the
8960 multimedia clock controller, except that gfx2d0/1 has been
removed and the gfx3d frequency is slightly faster when using the
newly introduced PLL15. We also add vcap clocks and a couple new
TV clocks.
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Diffstat (limited to 'include/dt-bindings')
| -rw-r--r-- | include/dt-bindings/clock/qcom,mmcc-msm8960.h | 8 | ||||
| -rw-r--r-- | include/dt-bindings/reset/qcom,mmcc-msm8960.h | 8 |
2 files changed, 16 insertions, 0 deletions
diff --git a/include/dt-bindings/clock/qcom,mmcc-msm8960.h b/include/dt-bindings/clock/qcom,mmcc-msm8960.h index 5868ef14a777..85041b28f97f 100644 --- a/include/dt-bindings/clock/qcom,mmcc-msm8960.h +++ b/include/dt-bindings/clock/qcom,mmcc-msm8960.h @@ -133,5 +133,13 @@ #define CSIPHY0_TIMER_CLK 116 #define PLL1 117 #define PLL2 118 +#define RGB_TV_CLK 119 +#define NPL_TV_CLK 120 +#define VCAP_AHB_CLK 121 +#define VCAP_AXI_CLK 122 +#define VCAP_SRC 123 +#define VCAP_CLK 124 +#define VCAP_NPL_CLK 125 +#define PLL15 126 #endif diff --git a/include/dt-bindings/reset/qcom,mmcc-msm8960.h b/include/dt-bindings/reset/qcom,mmcc-msm8960.h index ba36ec680118..11741113a841 100644 --- a/include/dt-bindings/reset/qcom,mmcc-msm8960.h +++ b/include/dt-bindings/reset/qcom,mmcc-msm8960.h @@ -89,5 +89,13 @@ #define CSI2_RESET 72 #define CSI_RDI1_RESET 73 #define CSI_RDI2_RESET 74 +#define GFX3D_AXI_RESET 75 +#define VCAP_AXI_RESET 76 +#define SMMU_VCAP_AHB_RESET 77 +#define VCAP_AHB_RESET 78 +#define CSI_RDI_RESET 79 +#define CSI_PIX_RESET 80 +#define VCAP_NPL_RESET 81 +#define VCAP_RESET 82 #endif |