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authorLinus Torvalds <torvalds@g5.osdl.org>2006-09-27 19:49:07 +0400
committerLinus Torvalds <torvalds@g5.osdl.org>2006-09-27 19:49:07 +0400
commitb98adfccdf5f8dd34ae56a2d5adbe2c030bd4674 (patch)
tree1807a029520f550dd4f90c95ad0063bceb00d645 /include/asm-sh/cpu-features.h
parentba21fe71725f94792330ebc3034ef2b35a36276f (diff)
parent33573c0e3243aaa38b6ad96942de85a1b713c2ff (diff)
downloadlinux-b98adfccdf5f8dd34ae56a2d5adbe2c030bd4674.tar.xz
Merge master.kernel.org:/pub/scm/linux/kernel/git/lethal/sh-2.6
* master.kernel.org:/pub/scm/linux/kernel/git/lethal/sh-2.6: (108 commits) sh: Fix occasional flush_cache_4096() stack corruption. sh: Calculate shm alignment at runtime. sh: dma-mapping compile fixes. sh: Initial vsyscall page support. sh: Clean up PAGE_SIZE definition for assembly use. sh: Selective flush_cache_mm() flushing. sh: More intelligent entry_mask/way_size calculation. sh: Support for L2 cache on newer SH-4A CPUs. sh: Update kexec support for API changes. sh: Optimized readsl()/writesl() support. sh: Report movli.l/movco.l capabilities. sh: CPU flags in AT_HWCAP in ELF auxvt. sh: Add support for 4K stacks. sh: Enable /proc/kcore support. sh: stack debugging support. sh: select CONFIG_EMBEDDED. sh: machvec rework. sh: Solution Engine SH7343 board support. sh: SH7710VoIPGW board support. sh: Enable verbose BUG() support. ...
Diffstat (limited to 'include/asm-sh/cpu-features.h')
-rw-r--r--include/asm-sh/cpu-features.h24
1 files changed, 24 insertions, 0 deletions
diff --git a/include/asm-sh/cpu-features.h b/include/asm-sh/cpu-features.h
new file mode 100644
index 000000000000..4bccd7c032f9
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+++ b/include/asm-sh/cpu-features.h
@@ -0,0 +1,24 @@
+#ifndef __ASM_SH_CPU_FEATURES_H
+#define __ASM_SH_CPU_FEATURES_H
+
+/*
+ * Processor flags
+ *
+ * Note: When adding a new flag, keep cpu_flags[] in
+ * arch/sh/kernel/setup.c in sync so symbolic name
+ * mapping of the processor flags has a chance of being
+ * reasonably accurate.
+ *
+ * These flags are also available through the ELF
+ * auxiliary vector as AT_HWCAP.
+ */
+#define CPU_HAS_FPU 0x0001 /* Hardware FPU support */
+#define CPU_HAS_P2_FLUSH_BUG 0x0002 /* Need to flush the cache in P2 area */
+#define CPU_HAS_MMU_PAGE_ASSOC 0x0004 /* SH3: TLB way selection bit support */
+#define CPU_HAS_DSP 0x0008 /* SH-DSP: DSP support */
+#define CPU_HAS_PERF_COUNTER 0x0010 /* Hardware performance counters */
+#define CPU_HAS_PTEA 0x0020 /* PTEA register */
+#define CPU_HAS_LLSC 0x0040 /* movli.l/movco.l */
+#define CPU_HAS_L2_CACHE 0x0080 /* Secondary cache / URAM */
+
+#endif /* __ASM_SH_CPU_FEATURES_H */