diff options
| author | AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> | 2025-11-24 14:06:54 +0300 |
|---|---|---|
| committer | AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> | 2026-01-08 12:27:49 +0300 |
| commit | c2488fecba681d632a3dbb6b2f33c39df2cb7be9 (patch) | |
| tree | c290d722ff9b1d463a599291a2f124b517ec7bfa /drivers | |
| parent | 23f1b4922a9135515e37d3bbad766e311845071f (diff) | |
| download | linux-c2488fecba681d632a3dbb6b2f33c39df2cb7be9.tar.xz | |
soc: mediatek: mtk-dvfsrc: Add and propagate DVFSRC bandwidth type
In preparation for adding support for DVFSRC Version 4, add a new
mtk_dvfsrc_bw_type enumeration, and propagate it from specific bw
setting callbacks to __dvfsrc_set_dram_bw_v1(), which will use it
to choose calculation multipliers and dividers in v4 callbacks.
Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/soc/mediatek/mtk-dvfsrc.c | 15 |
1 files changed, 11 insertions, 4 deletions
diff --git a/drivers/soc/mediatek/mtk-dvfsrc.c b/drivers/soc/mediatek/mtk-dvfsrc.c index 7708b07ab2d6..a684e405daf7 100644 --- a/drivers/soc/mediatek/mtk-dvfsrc.c +++ b/drivers/soc/mediatek/mtk-dvfsrc.c @@ -36,6 +36,13 @@ #define MTK_SIP_DVFSRC_INIT 0x0 #define MTK_SIP_DVFSRC_START 0x1 +enum mtk_dvfsrc_bw_type { + DVFSRC_BW_AVG, + DVFSRC_BW_PEAK, + DVFSRC_BW_HRT, + DVFSRC_BW_MAX, +}; + struct dvfsrc_bw_constraints { u16 max_dram_nom_bw; u16 max_dram_peak_bw; @@ -268,7 +275,7 @@ static void dvfsrc_set_vscp_level_v2(struct mtk_dvfsrc *dvfsrc, u32 level) } static void __dvfsrc_set_dram_bw_v1(struct mtk_dvfsrc *dvfsrc, u32 reg, - u16 max_bw, u16 min_bw, u64 bw) + int type, u16 max_bw, u16 min_bw, u64 bw) { u32 new_bw = (u32)div_u64(bw, 100 * 1000); @@ -285,21 +292,21 @@ static void dvfsrc_set_dram_bw_v1(struct mtk_dvfsrc *dvfsrc, u64 bw) { u64 max_bw = dvfsrc->dvd->bw_constraints->max_dram_nom_bw; - __dvfsrc_set_dram_bw_v1(dvfsrc, DVFSRC_SW_BW, max_bw, 0, bw); + __dvfsrc_set_dram_bw_v1(dvfsrc, DVFSRC_SW_BW, DVFSRC_BW_AVG, max_bw, 0, bw); }; static void dvfsrc_set_dram_peak_bw_v1(struct mtk_dvfsrc *dvfsrc, u64 bw) { u64 max_bw = dvfsrc->dvd->bw_constraints->max_dram_peak_bw; - __dvfsrc_set_dram_bw_v1(dvfsrc, DVFSRC_SW_PEAK_BW, max_bw, 0, bw); + __dvfsrc_set_dram_bw_v1(dvfsrc, DVFSRC_SW_PEAK_BW, DVFSRC_BW_PEAK, max_bw, 0, bw); } static void dvfsrc_set_dram_hrt_bw_v1(struct mtk_dvfsrc *dvfsrc, u64 bw) { u64 max_bw = dvfsrc->dvd->bw_constraints->max_dram_hrt_bw; - __dvfsrc_set_dram_bw_v1(dvfsrc, DVFSRC_SW_HRT_BW, max_bw, 0, bw); + __dvfsrc_set_dram_bw_v1(dvfsrc, DVFSRC_SW_HRT_BW, DVFSRC_BW_HRT, max_bw, 0, bw); } static void dvfsrc_set_opp_level_v1(struct mtk_dvfsrc *dvfsrc, u32 level) |