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| author | Imre Deak <imre.deak@intel.com> | 2025-08-05 10:36:47 +0300 |
|---|---|---|
| committer | Imre Deak <imre.deak@intel.com> | 2025-08-13 15:02:28 +0300 |
| commit | aaf01f66e0ee688f0df7eb941914c78fdecf1edd (patch) | |
| tree | 81ce00330acdc6f834571d81f8de2d0d14efe036 /drivers | |
| parent | 1ebc27248ea0b81f0023ca28894ac40183b86b7c (diff) | |
| download | linux-aaf01f66e0ee688f0df7eb941914c78fdecf1edd.tar.xz | |
drm/i915/tc: Use the cached max lane count value
Use the PHY's cached max lane count value on all platforms similarly to
LNL+. On LNL+ using the cached value is mandatory - since the
corresponding HW register field can get cleared by the time the value is
queried - on earlier platforms there isn't a problem with using the HW
register instead. Having a uniform way to query the value still makes
sense and it's also a bit more efficient, so do that.
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
Link: https://lore.kernel.org/r/20250805073700.642107-7-imre.deak@intel.com
Signed-off-by: Imre Deak <imre.deak@intel.com>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_tc.c | 4 |
1 files changed, 0 insertions, 4 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_tc.c b/drivers/gpu/drm/i915/display/intel_tc.c index 668ef139391b..f00fb6fc94d8 100644 --- a/drivers/gpu/drm/i915/display/intel_tc.c +++ b/drivers/gpu/drm/i915/display/intel_tc.c @@ -395,15 +395,11 @@ static void read_pin_configuration(struct intel_tc_port *tc) int intel_tc_port_max_lane_count(struct intel_digital_port *dig_port) { - struct intel_display *display = to_intel_display(dig_port); struct intel_tc_port *tc = to_tc_port(dig_port); if (!intel_encoder_is_tc(&dig_port->base)) return 4; - if (DISPLAY_VER(display) < 20) - return get_max_lane_count(tc); - return tc->max_lane_count; } |