diff options
| author | Carolina Jubran <cjubran@nvidia.com> | 2026-03-16 16:36:07 +0300 |
|---|---|---|
| committer | Jakub Kicinski <kuba@kernel.org> | 2026-03-19 05:05:14 +0300 |
| commit | 96aca5efec8a737057f31cd61586a4bb62af9829 (patch) | |
| tree | c7e3c0d258cf55e81bdf53d5db903a507ce38cf8 /drivers | |
| parent | f87ca3b905e2226b31510de1f53b5df6dd0f80aa (diff) | |
| download | linux-96aca5efec8a737057f31cd61586a4bb62af9829.tar.xz | |
net/mlx5: Support cross-timestamping on ARM architectures
Extend cross-timestamp support for ARM systems that implement the ARM
architected timer.
Signed-off-by: Carolina Jubran <cjubran@nvidia.com>
Reviewed-by: Shahar Shitrit <shshitrit@nvidia.com>
Signed-off-by: Tariq Toukan <tariqt@nvidia.com>
Reviewed-by: Simon Horman <horms@kernel.org>
Link: https://patch.msgid.link/20260316133607.8738-3-tariqt@nvidia.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c | 16 |
1 files changed, 9 insertions, 7 deletions
diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c b/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c index 3322814819ea..d785f1b4f2e1 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c @@ -38,10 +38,10 @@ #include "lib/eq.h" #include "en.h" #include "clock.h" -#ifdef CONFIG_X86 +#if defined(CONFIG_X86) || defined(CONFIG_ARM_ARCH_TIMER) #include <linux/timekeeping.h> #include <linux/cpufeature.h> -#endif /* CONFIG_X86 */ +#endif /* CONFIG_X86 || CONFIG_ARM_ARCH_TIMER */ #define MLX5_RT_CLOCK_IDENTITY_SIZE MLX5_FLD_SZ_BYTES(mrtcq_reg, rt_clock_identity) @@ -229,7 +229,7 @@ static int mlx5_set_mtutc(struct mlx5_core_dev *dev, u32 *mtutc, u32 size) MLX5_REG_MTUTC, 0, 1); } -#ifdef CONFIG_X86 +#if defined(CONFIG_X86) || defined(CONFIG_ARM_ARCH_TIMER) static bool mlx5_is_ptm_source_time_available(struct mlx5_core_dev *dev) { u32 out[MLX5_ST_SZ_DW(mtptm_reg)] = {0}; @@ -275,7 +275,8 @@ static int mlx5_mtctr_read(struct mlx5_core_dev *mdev, host = MLX5_GET64(mtctr_reg, out, first_clock_timestamp); *sys_counterval = (struct system_counterval_t) { .cycles = host, - .cs_id = CSID_X86_ART, + .cs_id = IS_ENABLED(CONFIG_X86) ? CSID_X86_ART : + CSID_ARM_ARCH_COUNTER, .use_nsecs = true, }; *device = MLX5_GET64(mtctr_reg, out, second_clock_timestamp); @@ -373,7 +374,7 @@ unlock: mlx5_clock_unlock(clock); return err; } -#endif /* CONFIG_X86 */ +#endif /* CONFIG_X86 || CONFIG_ARM_ARCH_TIMER */ static u64 mlx5_read_time(struct mlx5_core_dev *dev, struct ptp_system_timestamp *sts, @@ -1307,7 +1308,8 @@ static void mlx5_init_crosststamp(struct mlx5_core_dev *mdev, #if defined(CONFIG_X86) if (!boot_cpu_has(X86_FEATURE_ART)) return; - +#endif /* CONFIG_X86 */ +#if defined(CONFIG_X86) || defined(CONFIG_ARM_ARCH_TIMER) if (!MLX5_CAP_MCAM_REG3(mdev, mtptm) || !MLX5_CAP_MCAM_REG3(mdev, mtctr)) return; @@ -1316,7 +1318,7 @@ static void mlx5_init_crosststamp(struct mlx5_core_dev *mdev, if (expose_cycles) clock->ptp_info.getcrosscycles = mlx5_ptp_getcrosscycles; -#endif /* CONFIG_X86 */ +#endif /* CONFIG_X86 || CONFIG_ARM_ARCH_TIMER */ } static void mlx5_init_timer_clock(struct mlx5_core_dev *mdev) |