diff options
| author | Evan Quan <evan.quan@amd.com> | 2020-09-03 10:42:59 +0300 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2020-09-18 00:48:18 +0300 |
| commit | 911779e3fc282cbdcae96c70131e3fe89cd5c1bc (patch) | |
| tree | 3fdbb37384b92065ff15c6a2b58c6832abb8ab24 /drivers | |
| parent | ce2c00061b2810ff0523e34ab392893556e17bbf (diff) | |
| download | linux-911779e3fc282cbdcae96c70131e3fe89cd5c1bc.tar.xz | |
drm/amd/pm: add Raven2 watermark WmType setting
Which tells it's a normal pstate change or memory retraining.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Tested-by: Changfeng Zhu <Changfeng.Zhu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/gpu/drm/amd/pm/inc/smu10_driver_if.h | 3 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c | 11 |
2 files changed, 13 insertions, 1 deletions
diff --git a/drivers/gpu/drm/amd/pm/inc/smu10_driver_if.h b/drivers/gpu/drm/amd/pm/inc/smu10_driver_if.h index dea8fe93da63..c498158771cc 100644 --- a/drivers/gpu/drm/amd/pm/inc/smu10_driver_if.h +++ b/drivers/gpu/drm/amd/pm/inc/smu10_driver_if.h @@ -54,7 +54,8 @@ typedef struct { uint16_t MaxMclk; uint8_t WmSetting; - uint8_t Padding[3]; + uint8_t WmType; + uint8_t Padding[2]; } WatermarkRowGeneric_t; #define NUM_WM_RANGES 4 diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c index 9ee8cf8267c8..88792dba1759 100644 --- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c +++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c @@ -1181,8 +1181,19 @@ static int smu10_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr, struct smu10_hwmgr *data = hwmgr->backend; struct dm_pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges = clock_ranges; Watermarks_t *table = &(data->water_marks_table); + struct amdgpu_device *adev = hwmgr->adev; + int i; smu_set_watermarks_for_clocks_ranges(table,wm_with_clock_ranges); + + if (adev->apu_flags & AMD_APU_IS_RAVEN2) { + for (i = 0; i < NUM_WM_RANGES; i++) + table->WatermarkRow[WM_DCFCLK][i].WmType = (uint8_t)0; + + for (i = 0; i < NUM_WM_RANGES; i++) + table->WatermarkRow[WM_SOCCLK][i].WmType = (uint8_t)0; + } + smum_smc_table_manager(hwmgr, (uint8_t *)table, (uint16_t)SMU10_WMTABLE, false); data->water_marks_exist = true; return 0; |