drm/amdgpu: only set XCC 0 related reg for rlc autoload

For RLC autoload, only set XCC id 0 related register to trigger
rlc autoload, no need to trigger muti-times for muti-xcc.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

1 files changed, 31 insertions, 47 deletions

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c b/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c
index f741199e4348..fe903170db8c 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c
@@ -1043,7 +1043,6 @@ static int gfx_v12_1_rlc_backdoor_autoload_enable(struct amdgpu_device *adev)
 	uint32_t rlc_g_offset, rlc_g_size;
 	uint64_t gpu_addr;
 	uint32_t data;
-	int i, num_xcc = NUM_XCC(adev->gfx.xcc_mask);
 
 	/* RLC autoload sequence 2: copy ucode */
 	gfx_v12_1_rlc_backdoor_autoload_copy_sdma_ucode(adev);
@@ -1055,35 +1054,33 @@ static int gfx_v12_1_rlc_backdoor_autoload_enable(struct amdgpu_device *adev)
 	rlc_g_size = rlc_autoload_info[SOC24_FIRMWARE_ID_RLC_G_UCODE].size;
 	gpu_addr = adev->gfx.rlc.rlc_autoload_gpu_addr + rlc_g_offset - adev->gmc.vram_start;
 
-	for (i = 0; i < num_xcc; i++) {
-		WREG32_SOC15(GC, GET_INST(GC, i),
-			     regGFX_IMU_RLC_BOOTLOADER_ADDR_HI, upper_32_bits(gpu_addr));
-		WREG32_SOC15(GC, GET_INST(GC, i),
-			     regGFX_IMU_RLC_BOOTLOADER_ADDR_LO, lower_32_bits(gpu_addr));
-
-		WREG32_SOC15(GC, GET_INST(GC, i),
-			     regGFX_IMU_RLC_BOOTLOADER_SIZE, rlc_g_size);
-
-		if (adev->gfx.imu.funcs && (amdgpu_dpm > 0)) {
-			/* RLC autoload sequence 3: load IMU fw */
-			if (adev->gfx.imu.funcs->load_microcode)
-				adev->gfx.imu.funcs->load_microcode(adev);
-			/* RLC autoload sequence 4 init IMU fw */
-			if (adev->gfx.imu.funcs->setup_imu)
-				adev->gfx.imu.funcs->setup_imu(adev);
-			if (adev->gfx.imu.funcs->start_imu)
-				adev->gfx.imu.funcs->start_imu(adev);
-
-			/* RLC autoload sequence 5 disable gpa mode */
-			gfx_v12_1_xcc_disable_gpa_mode(adev, i);
-		} else {
-			/* unhalt rlc to start autoload without imu */
-			data = RREG32_SOC15(GC, GET_INST(GC, i), regRLC_GPM_THREAD_ENABLE);
-			data = REG_SET_FIELD(data, RLC_GPM_THREAD_ENABLE, THREAD0_ENABLE, 1);
-			data = REG_SET_FIELD(data, RLC_GPM_THREAD_ENABLE, THREAD1_ENABLE, 1);
-			WREG32_SOC15(GC, GET_INST(GC, i), regRLC_GPM_THREAD_ENABLE, data);
-			WREG32_SOC15(GC, GET_INST(GC, i), regRLC_CNTL, RLC_CNTL__RLC_ENABLE_F32_MASK);
-		}
+	WREG32_SOC15(GC, GET_INST(GC, 0),
+		     regGFX_IMU_RLC_BOOTLOADER_ADDR_HI, upper_32_bits(gpu_addr));
+	WREG32_SOC15(GC, GET_INST(GC, 0),
+		     regGFX_IMU_RLC_BOOTLOADER_ADDR_LO, lower_32_bits(gpu_addr));
+
+	WREG32_SOC15(GC, GET_INST(GC, 0),
+		     regGFX_IMU_RLC_BOOTLOADER_SIZE, rlc_g_size);
+
+	if (adev->gfx.imu.funcs && (amdgpu_dpm > 0)) {
+		/* RLC autoload sequence 3: load IMU fw */
+		if (adev->gfx.imu.funcs->load_microcode)
+			adev->gfx.imu.funcs->load_microcode(adev);
+		/* RLC autoload sequence 4 init IMU fw */
+		if (adev->gfx.imu.funcs->setup_imu)
+			adev->gfx.imu.funcs->setup_imu(adev);
+		if (adev->gfx.imu.funcs->start_imu)
+			adev->gfx.imu.funcs->start_imu(adev);
+
+		/* RLC autoload sequence 5 disable gpa mode */
+		gfx_v12_1_xcc_disable_gpa_mode(adev, 0);
+	} else {
+		/* unhalt rlc to start autoload without imu */
+		data = RREG32_SOC15(GC, GET_INST(GC, 0), regRLC_GPM_THREAD_ENABLE);
+		data = REG_SET_FIELD(data, RLC_GPM_THREAD_ENABLE, THREAD0_ENABLE, 1);
+		data = REG_SET_FIELD(data, RLC_GPM_THREAD_ENABLE, THREAD1_ENABLE, 1);
+		WREG32_SOC15(GC, GET_INST(GC, 0), regRLC_GPM_THREAD_ENABLE, data);
+		WREG32_SOC15(GC, GET_INST(GC, 0), regRLC_CNTL, RLC_CNTL__RLC_ENABLE_F32_MASK);
 	}
 
 	return 0;
@@ -1783,12 +1780,11 @@ static void gfx_v12_1_xcc_set_mec_ucode_start_addr(struct amdgpu_device *adev,
 	mutex_unlock(&adev->srbm_mutex);
 }
 
-static int gfx_v12_1_xcc_wait_for_rlc_autoload_complete(struct amdgpu_device *adev,
-							int xcc_id)
+static int gfx_v12_1_wait_for_rlc_autoload_complete(struct amdgpu_device *adev)
 {
 	uint32_t cp_status;
 	uint32_t bootload_status;
-	int i;
+	int i, xcc_id;
 
 	for (i = 0; i < adev->usec_timeout; i++) {
 		cp_status = RREG32_SOC15(GC, GET_INST(GC, 0), regCP_STAT);
@@ -1811,20 +1807,8 @@ static int gfx_v12_1_xcc_wait_for_rlc_autoload_complete(struct amdgpu_device *ad
 	}
 
 	if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
-		gfx_v12_1_xcc_set_mec_ucode_start_addr(adev, xcc_id);
-	}
-
-	return 0;
-}
-
-static int gfx_v12_1_wait_for_rlc_autoload_complete(struct amdgpu_device *adev)
-{
-	int xcc_id, r;
-
-	for (xcc_id = 0; xcc_id < NUM_XCC(adev->gfx.xcc_mask); xcc_id++) {
-		r = gfx_v12_1_xcc_wait_for_rlc_autoload_complete(adev, xcc_id);
-		if (r)
-			return r;
+		for (xcc_id = 0; xcc_id < NUM_XCC(adev->gfx.xcc_mask); xcc_id++)
+			gfx_v12_1_xcc_set_mec_ucode_start_addr(adev, xcc_id);
 	}
 
 	return 0;