diff options
| author | Samuel Holland <samuel@sholland.org> | 2021-09-03 01:57:50 +0300 |
|---|---|---|
| committer | Wim Van Sebroeck <wim@linux-watchdog.org> | 2021-10-26 22:31:08 +0300 |
| commit | 94213a39c3d8430297f52245d777b5c1ed627717 (patch) | |
| tree | cb5b1a3d5e4616cfdd72a13b04668800b2663c1b /drivers/watchdog/sunxi_wdt.c | |
| parent | 601db217916de339ddebeb3b6f024f09a275562a (diff) | |
| download | linux-94213a39c3d8430297f52245d777b5c1ed627717.tar.xz | |
watchdog: sunxi_wdt: Add support for D1
D1 adds a key field to the "CFG" and "MODE" registers, that must be set
to change the other bits. Add logic to set the key when updating those
registers.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Acked-by: Maxime Ripard <maxime@cerno.tech>
Reviewed-by: Guenter Roeck <linux@roeck-us.net>
Link: https://lore.kernel.org/r/20210902225750.29313-4-samuel@sholland.org
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Wim Van Sebroeck <wim@linux-watchdog.org>
Diffstat (limited to 'drivers/watchdog/sunxi_wdt.c')
| -rw-r--r-- | drivers/watchdog/sunxi_wdt.c | 20 |
1 files changed, 19 insertions, 1 deletions
diff --git a/drivers/watchdog/sunxi_wdt.c b/drivers/watchdog/sunxi_wdt.c index b50757882a98..6cf82922d3fb 100644 --- a/drivers/watchdog/sunxi_wdt.c +++ b/drivers/watchdog/sunxi_wdt.c @@ -48,6 +48,7 @@ struct sunxi_wdt_reg { u8 wdt_timeout_shift; u8 wdt_reset_mask; u8 wdt_reset_val; + u32 wdt_key_val; }; struct sunxi_wdt_dev { @@ -91,12 +92,14 @@ static int sunxi_wdt_restart(struct watchdog_device *wdt_dev, val = readl(wdt_base + regs->wdt_cfg); val &= ~(regs->wdt_reset_mask); val |= regs->wdt_reset_val; + val |= regs->wdt_key_val; writel(val, wdt_base + regs->wdt_cfg); /* Set lowest timeout and enable watchdog */ val = readl(wdt_base + regs->wdt_mode); val &= ~(WDT_TIMEOUT_MASK << regs->wdt_timeout_shift); val |= WDT_MODE_EN; + val |= regs->wdt_key_val; writel(val, wdt_base + regs->wdt_mode); /* @@ -109,6 +112,7 @@ static int sunxi_wdt_restart(struct watchdog_device *wdt_dev, mdelay(5); val = readl(wdt_base + regs->wdt_mode); val |= WDT_MODE_EN; + val |= regs->wdt_key_val; writel(val, wdt_base + regs->wdt_mode); } return 0; @@ -141,6 +145,7 @@ static int sunxi_wdt_set_timeout(struct watchdog_device *wdt_dev, reg = readl(wdt_base + regs->wdt_mode); reg &= ~(WDT_TIMEOUT_MASK << regs->wdt_timeout_shift); reg |= wdt_timeout_map[timeout] << regs->wdt_timeout_shift; + reg |= regs->wdt_key_val; writel(reg, wdt_base + regs->wdt_mode); sunxi_wdt_ping(wdt_dev); @@ -154,7 +159,7 @@ static int sunxi_wdt_stop(struct watchdog_device *wdt_dev) void __iomem *wdt_base = sunxi_wdt->wdt_base; const struct sunxi_wdt_reg *regs = sunxi_wdt->wdt_regs; - writel(0, wdt_base + regs->wdt_mode); + writel(regs->wdt_key_val, wdt_base + regs->wdt_mode); return 0; } @@ -176,11 +181,13 @@ static int sunxi_wdt_start(struct watchdog_device *wdt_dev) reg = readl(wdt_base + regs->wdt_cfg); reg &= ~(regs->wdt_reset_mask); reg |= regs->wdt_reset_val; + reg |= regs->wdt_key_val; writel(reg, wdt_base + regs->wdt_cfg); /* Enable watchdog */ reg = readl(wdt_base + regs->wdt_mode); reg |= WDT_MODE_EN; + reg |= regs->wdt_key_val; writel(reg, wdt_base + regs->wdt_mode); return 0; @@ -220,9 +227,20 @@ static const struct sunxi_wdt_reg sun6i_wdt_reg = { .wdt_reset_val = 0x01, }; +static const struct sunxi_wdt_reg sun20i_wdt_reg = { + .wdt_ctrl = 0x10, + .wdt_cfg = 0x14, + .wdt_mode = 0x18, + .wdt_timeout_shift = 4, + .wdt_reset_mask = 0x03, + .wdt_reset_val = 0x01, + .wdt_key_val = 0x16aa0000, +}; + static const struct of_device_id sunxi_wdt_dt_ids[] = { { .compatible = "allwinner,sun4i-a10-wdt", .data = &sun4i_wdt_reg }, { .compatible = "allwinner,sun6i-a31-wdt", .data = &sun6i_wdt_reg }, + { .compatible = "allwinner,sun20i-d1-wdt", .data = &sun20i_wdt_reg }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, sunxi_wdt_dt_ids); |