diff options
| author | John Youn <John.Youn@synopsys.com> | 2015-12-17 22:16:58 +0300 |
|---|---|---|
| committer | Felipe Balbi <balbi@ti.com> | 2015-12-22 20:58:34 +0300 |
| commit | 263b7fb557f797d9d4d1dcf93fb6bb2efc3f1d46 (patch) | |
| tree | 71d324a632fa9d1af12ce8a3a73c0a20d8ef676c /drivers/usb/dwc2/core.c | |
| parent | 1696d5ab99ef885ae62da5ad58f9eff16da7ff78 (diff) | |
| download | linux-263b7fb557f797d9d4d1dcf93fb6bb2efc3f1d46.tar.xz | |
usb: dwc2: Move reset into dwc2_get_hwparams()
The reset is required to get reset values of the hardware parameters but
the force mode is not. Move the base reset into dwc2_get_hwparams() and
do the reset and force mode afterwards.
Signed-off-by: John Youn <johnyoun@synopsys.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>
Diffstat (limited to 'drivers/usb/dwc2/core.c')
| -rw-r--r-- | drivers/usb/dwc2/core.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/drivers/usb/dwc2/core.c b/drivers/usb/dwc2/core.c index b700a47e026a..3b55635c878c 100644 --- a/drivers/usb/dwc2/core.c +++ b/drivers/usb/dwc2/core.c @@ -3120,6 +3120,9 @@ void dwc2_set_parameters(struct dwc2_hsotg *hsotg, /** * During device initialization, read various hardware configuration * registers and interpret the contents. + * + * This should be called during driver probe. It will perform a core + * soft reset in order to get the reset values of the parameters. */ int dwc2_get_hwparams(struct dwc2_hsotg *hsotg) { @@ -3128,6 +3131,7 @@ int dwc2_get_hwparams(struct dwc2_hsotg *hsotg) u32 hwcfg1, hwcfg2, hwcfg3, hwcfg4; u32 hptxfsiz, grxfsiz, gnptxfsiz; u32 gusbcfg = 0; + int retval; /* * Attempt to ensure this device is really a DWC_otg Controller. @@ -3147,6 +3151,10 @@ int dwc2_get_hwparams(struct dwc2_hsotg *hsotg) hw->snpsid >> 12 & 0xf, hw->snpsid >> 8 & 0xf, hw->snpsid >> 4 & 0xf, hw->snpsid & 0xf, hw->snpsid); + retval = dwc2_core_reset(hsotg); + if (retval) + return retval; + hwcfg1 = dwc2_readl(hsotg->regs + GHWCFG1); hwcfg2 = dwc2_readl(hsotg->regs + GHWCFG2); hwcfg3 = dwc2_readl(hsotg->regs + GHWCFG3); |