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authorMark Brown <broonie@kernel.org>2025-09-12 02:54:56 +0300
committerMark Brown <broonie@kernel.org>2025-09-12 02:54:56 +0300
commit9ca01e9226dbbb523b49b4e583e1d522977b4fe6 (patch)
tree630b0bbaf8c27dfb24c42570ec6e399700a4e662 /drivers/spi/spi-microchip-core-qspi.c
parent2c625f0fe2db4e6a58877ce2318df3aa312eb791 (diff)
parent6a129b2ca5c533aec89fbeb58470811cc4102642 (diff)
downloadlinux-9ca01e9226dbbb523b49b4e583e1d522977b4fe6.tar.xz
support for Amlogic SPI Flash Controller IP
Merge series from Xianwei Zhao <xianwei.zhao@amlogic.com>: This Flash Controller is derived by adding an SPI path to the original raw NAND controller. This controller supports two modes: raw mode and SPI mode. The raw mode has already been implemented in the community (drivers/mtd/nand/raw/meson_nand.c). This submission supports the SPI mode. Add the drivers and bindings corresponding to the SPI Flash Controller.
Diffstat (limited to 'drivers/spi/spi-microchip-core-qspi.c')
-rw-r--r--drivers/spi/spi-microchip-core-qspi.c12
1 files changed, 0 insertions, 12 deletions
diff --git a/drivers/spi/spi-microchip-core-qspi.c b/drivers/spi/spi-microchip-core-qspi.c
index 0a6f65c77eac..aafe6cbf2aea 100644
--- a/drivers/spi/spi-microchip-core-qspi.c
+++ b/drivers/spi/spi-microchip-core-qspi.c
@@ -531,10 +531,6 @@ error:
static bool mchp_coreqspi_supports_op(struct spi_mem *mem, const struct spi_mem_op *op)
{
- struct mchp_coreqspi *qspi = spi_controller_get_devdata(mem->spi->controller);
- unsigned long clk_hz;
- u32 baud_rate_val;
-
if (!spi_mem_default_supports_op(mem, op))
return false;
@@ -557,14 +553,6 @@ static bool mchp_coreqspi_supports_op(struct spi_mem *mem, const struct spi_mem_
return false;
}
- clk_hz = clk_get_rate(qspi->clk);
- if (!clk_hz)
- return false;
-
- baud_rate_val = DIV_ROUND_UP(clk_hz, 2 * op->max_freq);
- if (baud_rate_val > MAX_DIVIDER || baud_rate_val < MIN_DIVIDER)
- return false;
-
return true;
}