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| author | Andrew Jones <ajones@ventanamicro.com> | 2024-09-09 11:56:11 +0300 |
|---|---|---|
| committer | Thomas Gleixner <tglx@linutronix.de> | 2024-10-02 16:12:18 +0300 |
| commit | 4a1361e9a5c5dbb5c9f647762ae0cb1a605101fa (patch) | |
| tree | 8cc06fdab94ab8a7c5acbaae66b18cce55555ed9 /drivers/pinctrl/starfive/pinctrl-starfive-jh7110.h | |
| parent | 7f1f78b903c933617cbd352f9eafe9e3644f3b92 (diff) | |
| download | linux-4a1361e9a5c5dbb5c9f647762ae0cb1a605101fa.tar.xz | |
irqchip/riscv-imsic: Fix output text of base address
The "per-CPU IDs ... at base ..." info log is outputting a physical
address, not a PPN.
Fixes: 027e125acdba ("irqchip/riscv-imsic: Add device MSI domain support for platform devices")
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Anup Patel <anup@brainfault.org>
Link: https://lore.kernel.org/all/20240909085610.46625-2-ajones@ventanamicro.com
Diffstat (limited to 'drivers/pinctrl/starfive/pinctrl-starfive-jh7110.h')
0 files changed, 0 insertions, 0 deletions