diff options
| author | david.wu <david.wu@rock-chips.com> | 2017-02-10 13:23:47 +0300 |
|---|---|---|
| committer | Linus Walleij <linus.walleij@linaro.org> | 2017-03-14 16:42:20 +0300 |
| commit | 8b6c6f930da9d2f8f40f9c54a90efafb20fdad84 (patch) | |
| tree | 42defd79f92d07b10ec32e6dde9c95f6679ba424 /drivers/pinctrl/pinctrl-rockchip.c | |
| parent | 84b90e0cabf6b71a1d6292fbe936f669328a3881 (diff) | |
| download | linux-8b6c6f930da9d2f8f40f9c54a90efafb20fdad84.tar.xz | |
pinctrl: rockchip: Add 3bit width mux support
This patch supports 3bit width iomux type.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'drivers/pinctrl/pinctrl-rockchip.c')
| -rw-r--r-- | drivers/pinctrl/pinctrl-rockchip.c | 20 |
1 files changed, 17 insertions, 3 deletions
diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c index 7813599e43fa..09aff0e0eda8 100644 --- a/drivers/pinctrl/pinctrl-rockchip.c +++ b/drivers/pinctrl/pinctrl-rockchip.c @@ -75,6 +75,7 @@ enum rockchip_pinctrl_type { #define IOMUX_WIDTH_4BIT BIT(1) #define IOMUX_SOURCE_PMU BIT(2) #define IOMUX_UNROUTED BIT(3) +#define IOMUX_WIDTH_3BIT BIT(4) /** * @type: iomux variant using IOMUX_* constants @@ -538,14 +539,20 @@ static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin) ? info->regmap_pmu : info->regmap_base; /* get basic quadrupel of mux registers and the correct reg inside */ - mask = (bank->iomux[iomux_num].type & IOMUX_WIDTH_4BIT) ? 0xf : 0x3; reg = bank->iomux[iomux_num].offset; if (bank->iomux[iomux_num].type & IOMUX_WIDTH_4BIT) { if ((pin % 8) >= 4) reg += 0x4; bit = (pin % 4) * 4; + mask = 0xf; + } else if (bank->iomux[iomux_num].type & IOMUX_WIDTH_3BIT) { + if ((pin % 8) >= 5) + reg += 0x4; + bit = (pin % 8 % 5) * 3; + mask = 0x7; } else { bit = (pin % 8) * 2; + mask = 0x3; } ret = regmap_read(regmap, reg, &val); @@ -603,14 +610,20 @@ static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) ? info->regmap_pmu : info->regmap_base; /* get basic quadrupel of mux registers and the correct reg inside */ - mask = (bank->iomux[iomux_num].type & IOMUX_WIDTH_4BIT) ? 0xf : 0x3; reg = bank->iomux[iomux_num].offset; if (bank->iomux[iomux_num].type & IOMUX_WIDTH_4BIT) { if ((pin % 8) >= 4) reg += 0x4; bit = (pin % 4) * 4; + mask = 0xf; + } else if (bank->iomux[iomux_num].type & IOMUX_WIDTH_3BIT) { + if ((pin % 8) >= 5) + reg += 0x4; + bit = (pin % 8 % 5) * 3; + mask = 0x7; } else { bit = (pin % 8) * 2; + mask = 0x3; } spin_lock_irqsave(&bank->slock, flags); @@ -2359,7 +2372,8 @@ static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data( * Increase offset according to iomux width. * 4bit iomux'es are spread over two registers. */ - inc = (iom->type & IOMUX_WIDTH_4BIT) ? 8 : 4; + inc = (iom->type & (IOMUX_WIDTH_4BIT | + IOMUX_WIDTH_3BIT)) ? 8 : 4; if (iom->type & IOMUX_SOURCE_PMU) pmu_offs += inc; else |