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authorLinus Walleij <linus.walleij@linaro.org>2023-04-04 12:43:07 +0300
committerLinus Walleij <linus.walleij@linaro.org>2023-04-14 12:08:17 +0300
commit52066a53bd116a2f41d04d99b5095c02ad8cf953 (patch)
tree23f4b385aad98317bdefda1002fbed1032023047 /drivers/pinctrl/pinctrl-equilibrium.c
parentdcea54b7dad1b39757949d3e97a5eead161e8f0d (diff)
downloadlinux-52066a53bd116a2f41d04d99b5095c02ad8cf953.tar.xz
pinctrl: equilibrium: Convert to immutable irq_chip
Convert the driver to immutable irq-chip with a bit of intuition. Cc: Marc Zyngier <maz@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20230403-immutable-irqchips-v1-5-503788a7f6e6@linaro.org
Diffstat (limited to 'drivers/pinctrl/pinctrl-equilibrium.c')
-rw-r--r--drivers/pinctrl/pinctrl-equilibrium.c22
1 files changed, 14 insertions, 8 deletions
diff --git a/drivers/pinctrl/pinctrl-equilibrium.c b/drivers/pinctrl/pinctrl-equilibrium.c
index 99cf24eb67ae..5b5ddf7e5d0e 100644
--- a/drivers/pinctrl/pinctrl-equilibrium.c
+++ b/drivers/pinctrl/pinctrl-equilibrium.c
@@ -32,6 +32,7 @@ static void eqbr_gpio_disable_irq(struct irq_data *d)
raw_spin_lock_irqsave(&gctrl->lock, flags);
writel(BIT(offset), gctrl->membase + GPIO_IRNENCLR);
raw_spin_unlock_irqrestore(&gctrl->lock, flags);
+ gpiochip_disable_irq(gc, offset);
}
static void eqbr_gpio_enable_irq(struct irq_data *d)
@@ -42,6 +43,7 @@ static void eqbr_gpio_enable_irq(struct irq_data *d)
unsigned long flags;
gc->direction_input(gc, offset);
+ gpiochip_enable_irq(gc, offset);
raw_spin_lock_irqsave(&gctrl->lock, flags);
writel(BIT(offset), gctrl->membase + GPIO_IRNRNSET);
raw_spin_unlock_irqrestore(&gctrl->lock, flags);
@@ -161,6 +163,17 @@ static void eqbr_irq_handler(struct irq_desc *desc)
chained_irq_exit(ic, desc);
}
+static const struct irq_chip eqbr_irq_chip = {
+ .name = "gpio_irq",
+ .irq_mask = eqbr_gpio_disable_irq,
+ .irq_unmask = eqbr_gpio_enable_irq,
+ .irq_ack = eqbr_gpio_ack_irq,
+ .irq_mask_ack = eqbr_gpio_mask_ack_irq,
+ .irq_set_type = eqbr_gpio_set_irq_type,
+ .flags = IRQCHIP_IMMUTABLE,
+ GPIOCHIP_IRQ_RESOURCE_HELPERS,
+};
+
static int gpiochip_setup(struct device *dev, struct eqbr_gpio_ctrl *gctrl)
{
struct gpio_irq_chip *girq;
@@ -176,15 +189,8 @@ static int gpiochip_setup(struct device *dev, struct eqbr_gpio_ctrl *gctrl)
return 0;
}
- gctrl->ic.name = "gpio_irq";
- gctrl->ic.irq_mask = eqbr_gpio_disable_irq;
- gctrl->ic.irq_unmask = eqbr_gpio_enable_irq;
- gctrl->ic.irq_ack = eqbr_gpio_ack_irq;
- gctrl->ic.irq_mask_ack = eqbr_gpio_mask_ack_irq;
- gctrl->ic.irq_set_type = eqbr_gpio_set_irq_type;
-
girq = &gctrl->chip.irq;
- girq->chip = &gctrl->ic;
+ gpio_irq_chip_set_chip(girq, &eqbr_irq_chip);
girq->parent_handler = eqbr_irq_handler;
girq->num_parents = 1;
girq->parents = devm_kcalloc(dev, 1, sizeof(*girq->parents), GFP_KERNEL);