diff options
| author | Shawn Lin <shawn.lin@rock-chips.com> | 2017-05-23 22:32:56 +0300 |
|---|---|---|
| committer | Bjorn Helgaas <bhelgaas@google.com> | 2017-07-03 02:45:56 +0300 |
| commit | 45db3b7029a7c33a9ac6faaef50c35bbb8233369 (patch) | |
| tree | 77a93ad48cb913e75a6122f2c840d1886332afe2 /drivers/pci | |
| parent | 09cac05097535015f0a0d64c051f17fd8c65c6bb (diff) | |
| download | linux-45db3b7029a7c33a9ac6faaef50c35bbb8233369.tar.xz | |
PCI: rockchip: Configure RC's MPS setting
The default value of MPS for RC is 128 bytes, but actually it could support
256 bytes. So this patch fixes this issue.
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Diffstat (limited to 'drivers/pci')
| -rw-r--r-- | drivers/pci/host/pcie-rockchip.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/drivers/pci/host/pcie-rockchip.c b/drivers/pci/host/pcie-rockchip.c index c283633181d3..86413b884b4a 100644 --- a/drivers/pci/host/pcie-rockchip.c +++ b/drivers/pci/host/pcie-rockchip.c @@ -146,6 +146,9 @@ #define PCIE_RC_CONFIG_DCR_CSPL_SHIFT 18 #define PCIE_RC_CONFIG_DCR_CSPL_LIMIT 0xff #define PCIE_RC_CONFIG_DCR_CPLS_SHIFT 26 +#define PCIE_RC_CONFIG_DCSR (PCIE_RC_CONFIG_BASE + 0xc8) +#define PCIE_RC_CONFIG_DCSR_MPS_MASK GENMASK(7, 5) +#define PCIE_RC_CONFIG_DCSR_MPS_256 (0x1 << 5) #define PCIE_RC_CONFIG_LINK_CAP (PCIE_RC_CONFIG_BASE + 0xcc) #define PCIE_RC_CONFIG_LINK_CAP_L0S BIT(10) #define PCIE_RC_CONFIG_LCS (PCIE_RC_CONFIG_BASE + 0xd0) @@ -701,6 +704,11 @@ static int rockchip_pcie_init_port(struct rockchip_pcie *rockchip) rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_LINK_CAP); } + status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_DCSR); + status &= ~PCIE_RC_CONFIG_DCSR_MPS_MASK; + status |= PCIE_RC_CONFIG_DCSR_MPS_256; + rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_DCSR); + return 0; } |