diff options
| author | Alex Elder <elder@linaro.org> | 2022-09-27 01:09:23 +0300 |
|---|---|---|
| committer | Jakub Kicinski <kuba@kernel.org> | 2022-09-28 04:42:50 +0300 |
| commit | 12c7ea7dfd2c69f1db5bc19a330a5d2a7bfe44e8 (patch) | |
| tree | 153b6fa29e5325b0b017f4c0f3634b1b56ef772b /drivers/net/ipa/reg/ipa_reg-v4.5.c | |
| parent | a5ad8956f97ae1b97a3dd4923c8972573f2fc028 (diff) | |
| download | linux-12c7ea7dfd2c69f1db5bc19a330a5d2a7bfe44e8.tar.xz | |
net: ipa: define COMP_CFG IPA register fields
Create the ipa_reg_comp_cfg_field_id enumerated type, which
identifies the fields for the COMP_CFG IPA register.
Use IPA_REG_FIELDS() to specify the field mask values defined for
this register, for each supported version of IPA.
Use ipa_reg_bit() to build up the value to be written to this
register rather than using the *_FMASK preprocessor symbols.
Remove the definition of the *_FMASK symbols, along with the inline
functions that were used to encode certain fields whose position
and/or width within the register was dependent on IPA version.
Take this opportunity to represent all one-bit fields using BIT(x)
rather than GENMASK(x, x).
Signed-off-by: Alex Elder <elder@linaro.org>
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
Diffstat (limited to 'drivers/net/ipa/reg/ipa_reg-v4.5.c')
| -rw-r--r-- | drivers/net/ipa/reg/ipa_reg-v4.5.c | 25 |
1 files changed, 24 insertions, 1 deletions
diff --git a/drivers/net/ipa/reg/ipa_reg-v4.5.c b/drivers/net/ipa/reg/ipa_reg-v4.5.c index 433cf7575786..166b4f1fc2e1 100644 --- a/drivers/net/ipa/reg/ipa_reg-v4.5.c +++ b/drivers/net/ipa/reg/ipa_reg-v4.5.c @@ -7,7 +7,30 @@ #include "../ipa.h" #include "../ipa_reg.h" -IPA_REG(COMP_CFG, comp_cfg, 0x0000003c); +static const u32 ipa_reg_comp_cfg_fmask[] = { + /* Bit 0 reserved */ + [GSI_SNOC_BYPASS_DIS] = BIT(1), + [GEN_QMB_0_SNOC_BYPASS_DIS] = BIT(2), + [GEN_QMB_1_SNOC_BYPASS_DIS] = BIT(3), + /* Bit 4 reserved */ + [IPA_QMB_SELECT_CONS_EN] = BIT(5), + [IPA_QMB_SELECT_PROD_EN] = BIT(6), + [GSI_MULTI_INORDER_RD_DIS] = BIT(7), + [GSI_MULTI_INORDER_WR_DIS] = BIT(8), + [GEN_QMB_0_MULTI_INORDER_RD_DIS] = BIT(9), + [GEN_QMB_1_MULTI_INORDER_RD_DIS] = BIT(10), + [GEN_QMB_0_MULTI_INORDER_WR_DIS] = BIT(11), + [GEN_QMB_1_MULTI_INORDER_WR_DIS] = BIT(12), + [GEN_QMB_0_SNOC_CNOC_LOOP_PROT_DIS] = BIT(13), + [GSI_SNOC_CNOC_LOOP_PROT_DISABLE] = BIT(14), + [GSI_MULTI_AXI_MASTERS_DIS] = BIT(15), + [IPA_QMB_SELECT_GLOBAL_EN] = BIT(16), + [ATOMIC_FETCHER_ARB_LOCK_DIS] = GENMASK(20, 17), + [FULL_FLUSH_WAIT_RS_CLOSURE_EN] = BIT(21), + /* Bits 22-31 reserved */ +}; + +IPA_REG_FIELDS(COMP_CFG, comp_cfg, 0x0000003c); IPA_REG(CLKON_CFG, clkon_cfg, 0x00000044); |